Application Note. Slave Controller. Application Note ESC Comparison Feature and register comparison. (Online at

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1 Appliation Note Slave Controller Setion I Setion II Setion III Tehnology (Online at Register Desription (Online at Hardware Desription (Online at Appliation Note ESC Comparison Feature and register omparison Version 2.7 Date:

2 DOCUMENT ORGANIZATION DOCUMENT ORGANIZATION The Bekhoff EtherCAT Slave Controller (ESC) doumentation overs the following Bekhoff ESCs: EtherCAT for FPGAs EtherCAT for FPGAs The doumentation is organized in three setions. Setion I and setion II are ommon for all Bekhoff ESCs, Setion III is speifi for eah ESC variant. The latest doumentation is available at the Bekhoff homepage ( Setion I Tehnology (All ESCs) Setion I deals with the basi EtherCAT tehnology. Starting with the EtherCAT protool itself, the frame proessing inside EtherCAT slaves is desribed. The features and interfaes of the physial layer with its two alternatives Ethernet and EBUS are eplained afterwards. Finally, the details of the funtional units of an ESC like FMMU, SynManager, Distributed Cloks, Slave Information Interfae, Interrupts, Wathdogs, and so on, are desribed. Sine Setion I is ommon for all Bekhoff ESCs, it might desribe features whih are not available in a speifi ESC. Refer to the feature details overview in Setion III of a speifi ESC to find out whih features are available. Setion II Register Desription (All ESCs) Setion II ontains detailed information about all ESC registers. This setion is also ommon for all Bekhoff ESCs, thus registers, register bits, or features are desribed whih might not be available in a speifi ESC. Refer to the register overview and to the feature details overview in Setion III of a speifi ESC to find out whih registers and features are available. Setion III Hardware Desription (Speifi ESC) Setion III is ESC speifi and ontains detailed information about the ESC features, implemented registers, onfiguration, interfaes, pinout, usage, eletrial and mehanial speifiation, and so on. Espeially the Proess Data Interfaes (PDI) supported by the ESC are part of this setion. Additional Doumentation Appliation notes and utilities an also be found at the Bekhoff homepage. Pinout onfiguration tools for / are available. Additional information on EtherCAT s with latest updates regarding design flow ompatibility, FPGA devie support and known issues are also available. Trademarks Bekhoff, TwinCAT, EtherCAT, Safety over EtherCAT, TwinSAFE and XFC are registered trademarks of and liensed by Bekhoff Automation GmbH & Co. KG. Other designations used in this publiation may be trademarks whose use by third parties for their own purposes ould violate the rights of the owners. Patent Pending The EtherCAT Tehnology is overed, inluding but not limited to the following German patent appliations and patents: DE , DE , DE , DE with orresponding appliations or registrations in various other ountries. Dislaimer The doumentation has been prepared with are. The produts desribed are, however, onstantly under development. For that reason the doumentation is not in every ase heked for onsisteny with performane data, standards or other harateristis. In the event that it ontains tehnial or editorial errors, we retain the right to make alterations at any time and without warning. No laims for the modifiation of produts that have already been supplied may be made on the basis of the data, diagrams and desriptions in this doumentation. Copyright Bekhoff Automation GmbH & Co. KG 02/2017. The reprodution, distribution and utilization of this doument as well as the ommuniation of its ontents to others without epress authorization are prohibited. Offenders will be held liable for the payment of damages. All rights reserved in the event of the grant of a patent, utility model or design. Version Comment 1.0 Initial release DOCUMENT HISTORY 1.1 EtherCAT mode and slave ategory added Enhaned Link Detetion ompatibility added Editorial hanges 1.2 Different versions of ESCs added to omparison Update to EtherCAT Release V2.2.0/ ESC DL Control register address orreted : Register is only available if DC Syn Unit is enabled ( =1) s: Physial Read/Write Offset (00108:00109) is onfigurable ESC10 removed Editorial hanges 1.3 Added EtherCAT for Altera FPGAs V2.2.1 Editorial hanges 1. Update to and Editorial hanges 1.5 Update to EtherCAT for Altera FPGAs V2.3.0, Update to EtherCAT for FPGAs V2.03a Editorial hanges 1.6 Update to EtherCAT for Altera FPGAs V2.3.1, Update to EtherCAT for FPGAs V2.03b 1.7 Removed Enhaned Link Detetion EBUS support for / Update to EtherCAT for Altera FPGAs V2.3.2, Update to EtherCAT for FPGAs V Update to EtherCAT for Altera FPGAs V2..0, Update to EtherCAT for FPGAs V2.0a Added optional LED features Added FPGA design tool ompatibility 1.9 Updated FPGA design tool ompatibility 2.0 Update to EtherCAT for Altera FPGAs V3.0.2, Update to EtherCAT for FPGAs V3.00 Update to and Removed FPGA design tool ompatibility (moved to Data sheet addendum) 2.1 Update to EtherCAT for Altera FPGAs V2..3, Update to EtherCAT for FPGAs V2.0d 2.2 Update to EtherCAT for Altera FPGAs V3.0.5, Update to EtherCAT for FPGAs V3.00f 2.3 Update to EtherCAT for Altera FPGAs V3.0.6, Update to EtherCAT for FPGAs V3.00g 2. Editorial hanges 2.5 Update to EtherCAT for Altera FPGAs V3.0.9, Update to EtherCAT for FPGAs V3.00j 2.6 Update to EtherCAT for Altera FPGAs V2.. and V3.0.10, Update to EtherCAT IP Core for FPGAs V2.0e and 2.7 Added option names to register table, revised Distributed Cloks alternatives Altera is now Editorial hanges Slave Controller Appliation Note II

3 Overview 1 Overview This appliation note provides an overview of the features and available registers of the following Bekhoff EtherCAT Slave Controllers: EtherCAT for FPGAs (up to V2../V3.0.10) EtherCAT for FPGAs (up to V2.0e/) (Build 22) Refer to the ESC data sheets for further information. The ESC data sheets are available from the Bekhoff homepage ( Table 1: ESC Main Features Feature (latest) Ports 2-3 (eah EBUS/MII, ma. 1MII) 2- (eah EBUS/MII) 3 MII or 3 RGMII or 2 RMII FMMUs SynManagers RAM [Kbyte] Distributed Cloks 6 bit 6 bit bit 32 bit Digital I/O 16 bit 32 bit 8-32 bit 32 bit SPI Slave Yes Yes Yes Yes 8/16 bit µcontroller - Asyn/Syn Asyn Asyn On-hip bus - - Avalon AMBA AXI3 TM PLB AMBA AXI TM AMBA AXI LITE TM 2 MII - Slave Controller Appliation Note 1

4 ESC Features 2 ESC Features Feature V V2.. V2..3 V2..0 V2.3.1/ V2.3.2 V2.3.0 V2.2.1 V2.2.0 Table 2: ESC Features V2.0.0 V1.1.1 EtherCAT Ports Permanent ports Optional Bridge port 3 (EBUS or MII) EBUS ports MII ports /2/3 0/2/3 0/2 0/2 0/2 0/ /2/3 0/2 0/2 2 RMII ports /2 0/2 0/2 0/2 0/2 0/ /2 0/2 0/2 - RGMII ports Port Ports 0, 1 Ports 0, 1, Ports 0, 1, Ports 0, 1, 2, EtherCAT mode Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Diret Slave Category Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Full Slave Position addressing Node addressing Logial addressing Broadast addressing Physial Layer General Features FIFO Size onfigurable (00100[18:16]) FIFO Size default from SII EEPROM Auto-Forwarder heks CRC and SOF Forwarded RX Error indiation, detetion and Counter (00308:0030B) Lost Link Counter (00310:00313) Prevention of irulating frames Fallbak: Port 0 opens if are losed VLAN Tag and IP/UDP support Enhaned Link Detetion per port onfigurable EBUS Features Low Jitter Enhaned Link Detetion supported Enhaned Link Detetion ompatible EBUS signal validation LVDS Transeiver internal LVDS sample rate [MHz] 1,000 1,000 Remote link down signaling time onfigurable 00100[22] V j V2.0e V2.0d V2.0a V2.03d V2.03b/ V2.03a V2.00a V1.01b Slave Controller Appliation Note 2

5 ESC Features Feature General Ethernet Features (MII/RMII/RGMII) MII Management Interfae (00510:0051F) Supported PHY Address Offsets Individual port PHY addresses Port PHY addresses readable V V2.. V2..3 V2..0 V2.3.1/ V2.3.2 V2.3.0 V2.2.1 V2.2.0 V2.0.0 V /16 0/16 any any any any any any any any any any 0/16 0/16 0/16 any any any any any any any any any any 0/ Link Polarity onfigurable - User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi - Enhaned Link Detetion supported FX PHY support (native) PHY reset out signals Link detetion using PHY signal (LED) MI link status and onfiguration MI ontrollable by PDI (00516:00517) MI read error (00510[13]) MI PHY onfiguration update status (00518[5]) MI preamble suppression Additional MCLK Gigabit PHY onfiguration Gigabit PHY register 9 detetion relaed relaed relaed relaed relaed relaed relaed relaed FX PHY onfiguration Transparent Mode MII Features CLK25OUT as PHY lok soure Bootstrap TX Shift settings Automati TX Shift setting (with TX_CLK) TX Shift not neessary (PHY TX_CLK as lok soure) FIFO size redution steps PDI General Features Inreased PDI performane Etended PDI Configuration (00152:00153) PDI Error Counter (0030D) User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi - User logi User logi User logi PDI Error Code (0030E) CPU_CLK output (10, 20, 25 MHz) SOF, EOF, WD_TRIG and WD_STATE independent of PDI Available PDIs and PDI features depending on port onfiguration PDI seletion at run-time (SII EEPROM) PDI ative immediately (SII EEPROM settings ignored) PDI funtion aknowledge by write PDI Information register 001E:001F User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi V j V2.0e V2.0d V2.0a V2.03d V2.03b/ V2.03a V2.00a V1.01b - - Slave Controller Appliation Note 3

6 ESC Features Feature V V2.. V2..3 V2..0 V2.3.1/ V2.3.2 V2.3.0 V2.2.1 V2.2.0 V2.0.0 V1.1.1 Digital I/O PDI Digital I/O width [bits] 8/16 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 8/16/2/32 32 PDI Control register value (0010:0011) Control/Status signals: 2/0 1,2 7/ LATCH_IN 1,2 2 - SOF 1,2 2 - OUTVALID 1,2 2 - WD_TRIG 1,2 2 - OE_CONF OE_EXT EEPROM_ Loaded WD_STATE EOF Granularity of diretion onfiguration [bits] Bidiretional mode Output high-z if WD epired logi) logi) logi) logi) logi) logi) logi) logi) logi) logi) logi) logi) User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi - Output 0 if WD epired - Output with EOF Output with DC SynSignals - Input with SOF Input with DC SynSignals - SPI Slave PDI Ma. SPI lok [MHz] SPI modes onfigurable (00150[1:0]) SPI_IRQ driver onfigurable (00150[3:2]) SPI_SEL polarity onfigurable (00150[]) Data out sample mode onfigurable (00150[5]) 6-20 (SPI mode dep.) logi) 6-20 (SPI mode dep.) logi) V j logi) V2.0e logi) V2.0d logi) V2.0a logi) V2.03d logi) V2.03b/ logi) V2.03a logi) logi) V2.00a logi) V1.01b Busy signaling Wait State byte(s) - - Number of address etension byte(s) 2/ Byte SPI master support Etended error detetion (read busy violation) 1 any any any any any any any any any any any any any any any any any any any any any any any any any SPI_IRQ delay - Status indiation EEPROM_ Loaded signal logi) - 1 Shared ontrol/status signals: LATCH_IN/SOF and OUT_VALID/WD_TRIGGER 2 Availability depending on port onfiguration Slave Controller Appliation Note

7 ESC Features Feature Asynhronous µcontroller PDI Etended µc onfiguration bits 00150[7:], 00152:00153 ADR[15:13] available (000b if not available) V V2.. V2..3 V2..0 V2.3.1/ V2.3.2 V2.3.0 V2.2.1 V2.2.0 V2.0.0 V /16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit 8/16 bit - - EEPROM_Loaded signal RD polarity onfigurable (00150[7]) Read BUSY delay (00152[0]) Write after first edge (00152[2]) Default BUSY state Synhronous µcontroller PDI EEPROM_ Loaded signal - 8/16 bit On-Chip Bus PDI Avalon OPB PLB v AXI3 TM AXI TM AXI LITE TM Bus lok [MHz] (N=1,2,3, ) any any N*25 N*25 N*25 N*25 N*25 N*25 N*25 N*25 N*25 N*25 25 any any N*25 N*25 N*25 N*25 N*25 N*25 N*25 N*25 N*25 Data bus width [bits] 8/16/ 8/16/ /16/ 8/16/ Prefeth yles 1 1 1/2/ 1/2/ 1/2/ 1/2/ 1/2/ 1/2/ 1/2/ 1/2/ 1/2/ 1 1 DC SynSignals available diretly and as IRQ Bus lok multiplier in register 00150[6:0] EEPROM_ Loaded signal EtherCAT Bridge (port 3, EBUS/MII) V j V2.0e 1/2/ (OPB) V2.0d 1/2/ (OPB) V2.0a 1/2/ (OPB) V2.03d 1/2/ (OPB) V2.03b/ 1/2/ (OPB) V2.03a 1/2/ (OPB) V2.00a V1.01b 1/2/ 1/2/ General Purpose I/O GPO bits GPI bits GPIO available independent of PDI or port onfiguration GPIO available without PDI Conurrent aess to GPO by ECAT and PDI ESC Information Basi Information (00000:00006) Port Desriptor (00007) - ESC Features supported (00008:00009) Etended ESC Feature Availability in User RAM (00F80 ff.) Write Protetion (00020:00031) Slave Controller Appliation Note 5

8 ESC Features Feature Data Link Layer Features V V2.. V2..3 V2..0 V2.3.1/ V2.3.2 V2.3.0 V2.2.1 V2.2.0 V2.0.0 V1.1.1 ECAT Reset (0000) PDI Reset (0001) ESC DL Control (00100:00103) bytes EtherCAT only mode (00100[0]) Temporary loop ontrol (00100[1]) FIFO Size onfigurable (00100[18:16]) Configured Station Address (00010:00011) Configured Station Alias (00100[2], 00012:00013) Physial Read/Write Offset (00108:00109) Appliation Layer Features Etended AL Control/Status bits (00120[15:5], 00130[15:5]) AL Status Emulation (0010[8]) AL Status Code (0013:00135) Interrupts ECAT Event Mask (00200:00201) AL Event Mask (0020:00207) ECAT Event Request (00210:00211) AL Event Request (00220:00223) SynManager ativation hanged (00220[]) SynManager wathdog epiration (00220[6]) Error Counters RX Error Counter (00300:00307) Forwarded RX Error Counter (00308:0030B) ECAT Proessing Unit Error Counter (0030C) PDI Error Counter (0030D) Lost Link Counter (00310:00313) Wathdog Wathdog Divider onfigurable (0000:0001) 2/ 2/ 2/ 2/ 2/ 2/ 2/ 2 2/ 2/ 2/ 2/ 2/ 2/ Wathdog Proess Data Wathdog PDI Wathdog Counter Proess Data (002) Wathdog Counter PDI (003) V j V2.0e V2.0d V2.0a V2.03d V2.03b/ V2.03a V2.00a V1.01b Slave Controller Appliation Note 6

9 ESC Features Feature SII EEPROM Interfae (00500:0050F) EEPROM sizes supported EEPROM size refleted in 00502[7] EEPROM ontrollable by PDI EEPROM Emulation by PDI EEPROM Emulation CRC error 00502[11] PDI writable Read data bytes (00502[6]) Internal Pull-Ups for EEPROM_CLK and EEPROM_DATA V V2.. V2..3 V2..0 V2.3.1/ V2.3.2 V2.3.0 V2.2.1 V2.2.0 V2.0.0 V Kbyte User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi - I2C base address FMMUs Bit-oriented operation SynManagers Wathdog trigger generation for 1 Byte Mailbo onfiguration independent of reading aess SynManager Event Times (+08[7:6]) Buffer state (+05[7:6]) SynManager Sequential mode SynManager deativation delay Distributed Cloks Width Syn/Lath signals SynManager Event Times (009F0:009FF) (0-2 Syn- Signals, 0-2 Lath- (0-2 Syn- Signals, 0-2 Lath- (2 Syn- Lath- (2 Syn- Lath- (2 Syn- Lath- (2 Syn- Lath- (2 Syn- Lath- (2 Syn- Lath- (2 Syn- Lath- (2 Syn- Lath- (2 Syn- Lath- (2 Syn- Lath DC Reeive Times if DC on if DC on if DC on if DC on if DC on if DC on DC Time Loop Control ontrollable by PDI DC Syn/Lath ativation (0010[11:10]) Propagation delay measurement with traffi (BWR/FPWR 0900 deteted at eah port) LathSignal state in Lath Status register (009AE:009AF) SynSignal Auto- Ativation (00981[3]) SynSignal 32 or 6 bit Start Time (00981[]) SynSignal Late Ativation (00981[6:5]) SynSignal debug pulse (00981[7]) SynSignal Ativation State 0098) Reset filters after writing filter depth Kbyte- (2 Syn- Lath- (0-2 Syn- Signals, 0-2 Lath- V j (0-2 Syn- Signals, 0-2 Lath- V2.0e (2 Syn- Lath- V2.0d (2 Syn- Lath- V2.0a (2 Syn- Lath- V2.03d (2 Syn- Lath- V2.03b/ (2 Syn- Lath- V2.03a (2 Syn- Lath- (2 Syn- Lath- V2.00a (2 Syn- Lath- V1.01b (2 Syn- Lath- 16 Kbyte- 2 3 SYNC/LATCH[1] available if no MII port is used. Slave Controller Appliation Note 7

10 ESC Features Feature ESC Speifi Registers (00E00:00EFF) V V2.. V2..3 V2..0 V2.3.1/ V2.3.2 V2.3.0 V2.2.1 V2.2.0 V2.0.0 V1.1.1 Produt and Vendor ID POR Values FPGA Update (online) Proess RAM and User RAM Proess RAM (01000 ff.) [Kbyte] User RAM (00F80:00FFF) Etended ESC Feature Availability in User RAM RAM initialization - - Additional EEPROMs SII EEPROM (I²C) FPGA onfiguration EEPROM LED Signals - - RUN LED RUN LED override Link/Ativity() LED per port PERR() LED per port Devie ERR LED STATE_RUN LED Optional LED states RUN LED: Bootstrap RUN LED: Booting RUN LED: Devie identifiation RUN LED: loading SII EEPROM Error LED: SII EEPROM loading error Error LED: Invalid hardware onfiguration Error LED: Proess data wathdog timeout Error LED: PDI wathdog timeout Error LED: Error Indiation 00130[] Link/Ativity: port losed Link/Ativity: loal autonegotiation error Link/Ativity: remote auto-negotiation error Link/Ativity: unknown PHY auto-negotiation error LED test Clok supply Crystal Crystal osillator - TX_CLK from PHY 25ppm lok soure auray Internal PLL User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi User logi Power Supply Voltages 3 2 FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. 2 I/O Voltage FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. 3.3 V FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. 3.3V / 5V tolerant - - FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. - 5 V () () FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. - Core Voltage 2.5V 2.5V FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. 1.5V Internal LDOs LDO supply voltage 3.3V/5V 3.3V/5V Core Voltage I/O Voltage - V j V2.0e V2.0d V2.0a V2.03d V2.03b/ V2.03a V2.00a V1.01b Slave Controller Appliation Note 8

11 ESC Features Feature V V2.. V2..3 V2..0 V2.3.1/ V2.3.2 V2.3.0 V2.2.1 V2.2.0 V2.0.0 V1.1.1 Pakage QFN8 BGA128 FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. BGA256 Size [mm²] FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep. FPGA dep Original Release date 11/2006 3/2007 1/2015 3/2013 1/2015 7/2013 3/2011 2/ /2009 6/2009 6/2008 8/2007 1/ /2006 7/2006 1/2015 5/2013 1/2015 7/2013 3/2011 6/2010 2/ /2009 6/2008 8/2007 1/2007 7/2005 Configuration and Pinout alulator (XLS) Register Configuration fied fied individual individual individual individual individual individual individual individual individual individual 3 sets (s/m/l) 3 sets (s/m/l) 3 sets (s/m/l) V j V2.0e V2.0d V2.0a V2.03d V2.03b/ V2.03a V2.00a individual individual individual individual individual individual individual individual individual individual Liense devie required Evaluation version Vendor ID pakage Internal tri-strate drivers IPCore onfiguration tool XPS IP ores Eample designs/ pre-synthesized timelimited evaluation ore inluded in setup - - / 6/6 3/3 5/ 5/ 7/3 7/3 7/3 7/3 /- /- /- 2/- 3/3 /3 2/1 /2 /2 3/1 3/1 3/1 /1 3/- 3/- - FB1120 Digital I/O /- /- /- /- /- /- /- / FB1120 SPI /- /- /- /- /- /- /- / FB1122 Digital I/O - / - / / / / / / FB1122 SPI - / - /- / DBC2C20 Digital I/O / / / / /- /- / DBC2C20 NIOS /- /- /- /- /- /- / DBC3C0 Digital I/O / / / / / / / / / DBC3C0 NIOS /- /- /- / DBCCE55 NIOS / / / / / DE2-115 NIOS MII / / / / / DE2-115 NIOS RGMII / / FB1130 Digital I/O / / / / / / /- /- FB1130 SPI /- /- /- /- /- /- /- /- FB1130 PLB /- /- /- /- / FB1130 OPB /- /- /- FB1130 PLB2OPB /- - - LX150T PLB2AXI / / / LX150T Digital I/O / / / LX150T AXI / / ZC702 AXI (PlanAhead) / ZC702 AXI (Vivado) / / V1.01b 3 sets (s/m/l) fied Table 3: ESC Feature Legend Symbol Desription available - not available onfigurable User logi Funtionality an be added by user logi inside the FPGA red Feature hanged in this version Slave Controller Appliation Note 9

12 ESC Registers 3 ESC Registers Address Length (Byte) Desription V3.0.10, V3.00- V2..0-V2../ V2.0a-V2.0e Table : ESC Registers V2.3.0-V2.3.2/ V2.03a-V2.03d V2.2.1/V2.2.0/ V2.0.0/V2.00a V1.1.1/V1.01b Type Revision 00002: Build FMMUs supported SynManagers supported RAM Size Port Desriptor : ESC Features supported 00010: Configured Station Address 00012: Configured Station Alias Option Write Register Enable Write Protetion Write Register Protetion Write Protetion ESC Write Enable Write Protetion ESC Write Protetion Write Protetion ESC Reset ECAT RESET slave by ECAT/PDI ESC Reset PDI RESET slave by ECAT/PDI 00100: ESC DL Control 00102: Etended ESC DL Control r/ r/ r/ r/ r/ r/ r r r r r r 00108: Physial Read/Write Offset Read/Write Offset 00110: ESC DL Status bits [:0] AL Control 00120: AL Control bits [:0] AL Status 00130: AL Status : AL Status Code AL Status Code Register RUN LED Override Etended RUN/ERR LED ERR LED Override Etended RUN/ERR LED PDI Control ESC Configuration 001E:001F 2 PDI Information PDI Information Register PDI Configuration DC Syn/Lath Configuration 00152: Etended PDI Configuration Slave Controller Appliation Note 10

13 ESC Registers Address Length (Byte) Desription V3.0.10, V3.00- V2..0-V2../ V2.0a-V2.0e V2.3.0-V2.3.2/ V2.03a-V2.03d V2.2.1/V2.2.0/ V2.0.0/V2.00a V1.1.1/V1.01b 00200: ECAT Event Mask Option 0020:00207 PDI AL Event Mask r/ r/ r/ r/ r/ r r r AL Event Mask Register 00210: ECAT Event Request 00220:00223 AL Event Request 00300: R Error Counter[3:0] 00308:0030B 1 Forwarded R Error ounter[3:0] C 1 ECAT Proessing Unit Error Counter EPU and PDI Error Counter 0030D 1 PDI Error Counter EPU and PDI Error Counter 0030E 1 PDI Error Code EPU and PDI Error Counter 00310: Lost Link Counter[3:0] Lost Link Counter 0000: Wathdog Divider r/ r/ r/ r/ r/ r r r Etended Wathdog 0010: Wathdog Time PDI Etended Wathdog 0020: Wathdog Time Proess Data 000:001 2 Wathdog Status Proess Data Wathdog Counter Proess Data Wathdog Counter Wathdog Counter PDI Wathdog Counter 00500:0050F 16 SII EEPROM Interfae 00510: MII Management Interfae PHY Management Interfae 00516: MII Management Aess State PHY Management Interfae 00518:0051B PHY Port Status[3:0] Link state and PHY onfiguration through MI 000:006FC 1613 FMMU[15:0] Number of FMMU 00800:0087F 168 SynManager[15:0] Number of SynManagers Slave Controller Appliation Note 11

14 ESC Registers Address Length (Byte) Desription V3.0.10, V3.00- V2..0-V2../ V2.0a-V2.0e V2.3.0-V2.3.2/ V2.03a-V2.03d V2.2.1/V2.2.0/ V2.0.0/V2.00a V1.1.1/V1.01b Option 00900:0090F DC Reeive Times RT RT RT RT RT RT RT RT RT RT DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 00910: DC System Time SL DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 00918:0091F 8 DC Reeive Time EPU SL DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 00920: DC System Time Offset SL DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 00928:0092B DC System Time Delay SL DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 0092C:0092F DC System Time Differene SL DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 00930: DC Speed Counter Start SL DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 00932: DC Speed Counter Diff SL DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend DC System Time Differene Filter Depth DC Speed Counter Filter Depth SL DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend SL DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend DC Reeive Time Lath mode DC Cyli Unit Control S SL DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend DC Ativation S S DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 00982: DC Pulse length of SynSignals S S DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend DC Ativation Status - - S DC DC DC DC DC DC DC DC DC Refer to legend 0098E 1 DC SYNC0 Status S S0 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 0098F 1 DC SYNC1 Status S S1 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 00990: DC Net Time Cyli Operation/Net SYNC0 Pulse S S0 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 00998:0099F 8 DC Net SYNC1 Pulse S S1 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 009A0:009A3 DC SYNC0 Cyle Time S S0 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 009A:009A7 DC SYNC1 Cyle Time S S1 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 009A8 1 DC Lath0 Control L L0 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 009A9 1 DC Lath1 Control L L1 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 009AE 1 DC Lath0 Status L L0 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 009AF 1 DC Lath1 Status L L1 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 009B0:009B7 8 DC Lath0 Positive Edge L L0 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 009B8:009BF 8 DC Lath0 Negative Edge L L0 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 009C0:009C7 8 DC Lath1 Positive Edge L L1 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 009C7:009CF 8 DC Lath1 Negative Edge L L1 DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC DC Refer to legend 009F0:009F3 DC EtherCAT Buffer Change Event Time 009F8:009FB DC PDI Buffer Start Event Time 009FC:009FF DC PDI Buffer Change Event Time - SL ET ET ET ET ET ET ET ET ET ET ET ET ET - - DC - - DC - - DC - Refer to legend - SL ET ET ET ET ET ET ET ET ET ET ET ET ET - - DC - - DC - - DC - Refer to legend - SL ET ET ET ET ET ET ET ET ET ET ET ET ET - - DC - - DC - - DC - Refer to legend Slave Controller Appliation Note 12

15 ESC Registers Address Length (Byte) Desription V3.0.10, V3.00- V2..0-V2../ V2.0a-V2.0e V2.3.0-V2.3.2/ V2.03a-V2.03d V2.2.1/V2.2.0/ V2.0.0/V2.00a V1.1.1/V1.01b 00E00:00E03 Power-On Values [Bits] E00:00E07 8 Produt ID E08:00E0F 8 Vendor ID E10 1 ESC Health Status Option 00F00:00F03 Digital I/O Output Data io io io io io io io io io io io io io io io io io io io io io io Seleted PDI 00F10:00F17 8 General Purpose Outputs [Byte] Number of GPIOs 00F18:00F1F 8 General Purpose Inputs [Byte] Number of GPIOs 00F80:00FFF 128 User RAM 01000:01003 Digital I/O Input Data io io io io io io io io io io io io io io io io io io io io io io io io io Proess Data RAM ff. Proess Data RAM [Kbyte] Proess Data RAM Table 5: ESC Register Legend Symbol Desription EEPROM setting EEPROM setting Option sine V3.0.0/V3.00 Option V2.2.0/- V2../V2.0e Option V2.0.0/V2.00a Option - V1.1.1/V1.01b Available - Not available r Read only Configurable RT DC Reeive Times enabled Reeive Times Reeive Times Distributed loks Distributed loks DC DC Time Loop Control enabled 00000[10]=1, or 00000[11]=1 SL DC SYNC Out Unit and/or Lath In Unit enabled 00000[10]=1, or 00000[11]=1 Distributed loks Distributed loks Distributed loks Distributed loks DC SynSignals>0, or DC LathSignals>0 Distributed loks Distributed loks Distributed loks S DC SYNC Out Unit enabled 00000[10]=1 DC SynSignals>0 Distributed loks Distributed loks Distributed loks S# DC SYNC Out Unit instane # enabled DC SynSignals Distributed loks Distributed loks Distributed loks L DC Lath In Unit enabled 00000[11]=1 DC LathSignals>0 Distributed loks Distributed loks Distributed loks L# DC Lath In Unit instane # enabled DC LathSignals Distributed loks Distributed loks Distributed loks ET DC SynManager Event Times are enabled 00000[10]=1, or 00000[11]=1 SynManager Event Times SynManager Event Times SynManager Event Times Distributed loks io red Available if Digital I/O PDI is seleted Register hanged in this version Slave Controller Appliation Note 13

16 Appendi Appendi.1 Support and Servie Bekhoff and our partners around the world offer omprehensive support and servie, making available fast and ompetent assistane with all questions related to Bekhoff produts and system solutions..1.1 Bekhoff s branh offies and representatives Please ontat your Bekhoff branh offie or representative for loal support and servie on Bekhoff produts! The addresses of Bekhoff's branh offies and representatives round the world an be found on her internet pages: You will also find further doumentation for Bekhoff omponents there..2 Bekhoff Headquarters Bekhoff Automation GmbH & Co. KG Huelshorstweg Verl Germany Phone: +9 (0) Fa: +9 (0) Web: Bekhoff Support info@bekhoff.om Support offers you omprehensive tehnial assistane, helping you not only with the appliation of individual Bekhoff produts, but also with other, wide-ranging servies: world-wide support design, programming and ommissioning of omple automation systems and etensive training program for Bekhoff system omponents Hotline: +9 (0) Fa: +9 (0) Bekhoff Servie support@bekhoff.om The Bekhoff Servie Center supports you in all matters of after-sales servie: on-site servie repair servie spare parts servie hotline servie Hotline: +9 (0) Fa: +9 (0) servie@bekhoff.om Slave Controller Appliation Note 1