FINAL PRODUCT/PROCESS CHANGE NOTIFICATION #16476

Transcription

1 FIN PRODUCT/PROCESS CHNGE NOTIFICTION # Issue Date: 9-ay-200 TITE: Qualification of Serial I 2 C EEPRO devices CT2C0, CT2C0, CT2C, CT2C2 and CT2C for fabrication at ON Semiconductor s Gresham, Oregon Wafer Fab, and marking updates for product using Gresham die, to differentiate from product using the current OKI Semiconductor die. PROPOSED FIRST SHIP DTE: 20-ug-200 Customers needing additional time to qualify Gresham die will be given 0 more days. FFECTED CHNGE CTEGOR(S): CT2C0, CT2C0, CT2C, CT2C2 and CT2C (all Packages, all Temperatures) FOR N QUESTIONS CONCERNING THIS NOTIFICTION: Contact your local ON Semiconductor Sales Office or Denisa Stefan<denisa.stefan@onsemi.com> SPES: Samples available per ffected Device ist table on Page Contact your local ON Semiconductor Sales Office DDITION REIBIIT DT: vailable Contact your local ON Semiconductor Sales Office or Tony uciani<tony.luciani@onsemi.com> NOTIFICTION TPE: Final Product/Process Change Notification (FPCN) Final change notification sent to customers. FPCNs are issued at least 90 days prior to implementation of the change. ON Semiconductor will consider this change approved unless specific conditions of acceptance are provided in writing within 0 days of receipt of this notice. To do so, contact <quality@onsemi.com>. DESCRIPTION ND PURPOSE: ON Semiconductor is pleased to announce that, as part of its ongoing effort to improve product availability, the Serial I 2 C EEPRO devices CT2C0, CT2C0, CT2C, CT2C2 and CT2C are now qualified for production in the 0.5 µm COS EE process at ON Semiconductor s -inch Wafer Fab in Gresham, Oregon, US. The Gresham Wafer Fab is ISO900:200, ISO/TS99:2009 and ISO00:200 certified. Wafers for these devices will also continue to be supplied by our foundry partner OKI Semiconductor, Japan from a -inch line running a 0.5 µm COS EE process. Gresham wafers will supplement the OKI wafer supply. Package marking for product using Gresham die will be updated to eliminate obsolete references and to provide for easier identification of device and die revision, as requested by our customers. Package marking for product using OKI die will stay unchanged. This notification and acceptance thereof, allows for the use of either Gresham or OKI die in future shipments under the same OPN. Issue Date: 9-ay-200 Rev. 0-Jan-200 Page of 0

2 FIN PRODUCT/PROCESS CHNGE NOTIFICTION # REIBIIT DT SUR: QTP: 0900, CT2C Rev F, Gresham 0.5um Process Product Qual ot Number ssy ot Wfr ot CT2C lot WE025C G299# 2 CT2C lot2 G299 #2 CT2C lot G5090 #22 CT2C02 lot WE099FS 55NSEC5 CT2C02 lot 5 WE025BFS Q029SED Notes: ) Packages are suggested, and may change, with the exception of G which must be surface mount. 2) Family data from higher density products may be applicable when available Package ot Number Samples hrs 0hrs 000hrs HTO 0hrs, 50C release lot PSS High Temp Op ife Per J0 SOIC lot PSS PSS PSS (x) Tritemp test before and after lot 5 PSS PSS PSS Package ot Number Samples 2hrs EFR Per EC-Q00-00 lot 00 PSS Early ife Failure Rate HTO conditions, 2hrs, 50C SOIC lot 00 PSS Room/Hot testing before and after lot 5 00 PSS Package ot Number Samples 00k 200k 00k 00k 500k EDR NV Endurance Per JESD22- SOIC 0/Q Cycles lot PSS PSS PSS PSS PSS Package ot Number Samples 00k 00k 00k 900k Room/Hot test before and after SOIC lot PSS PSS PSS PSS PSS Wafer evel Endurance Cycles Wafer ot Number Samples lot2 PSS lot PSS EDR NV Data Retention Data ot Number Samples hrs hrs 500hrs 000hrs Package evel Per Q hrs, 50C "00" lot PSS PSS PSS Room/Hot test before Cycling Precon to 00k and after "FF" lot PSS PSS PSS Wafer evel Data ot Number Samples 00hrs Bake at 225C, 00hrs Endurance Preconditioning: 500k Cycles "00" Wafer evel lot2 PSS Wafer evel lot PSS "FF" Wafer evel lot2 PSS Wafer evel lot PSS Issue Date: 9-ay-200 Rev. 0-Jan-200 Page 2 of 0

3 FIN PRODUCT/PROCESS CHNGE NOTIFICTION # REIBIIT DT QTP 0900 Cont d Package ot Number ss 500V 000V 500V 2000V ESD Human Body odel EC Q SOIC lot /level PSS PSS PSS PSS lot, units per level Package ot Number ss 2500V 000V 500v 000v SOIC lot /level PSS PSS PSS PSS Package ot Number ss 50V 00V 50V 200V ESD achine odel EC Q00-00 SOIC lot /level PSS PSS PSS PSS lot, units per level Package ot Number ss 00ma U atch Up 25C 25C ( x ) per EC-Q00-00 SOIC lot PSS PSS Room / Hot testing after U test Package ot Number ss Result CHR Per EC-Q00 lot 0 PSS Characterization SOIC lot 2 0 PSS ( x 0) lot 0 /5/200 EECTRIC CHRCTERISTIC SUR: Gresham die are 00% compatible to the corresponding OKI die in the sense of meeting existing data sheet specifications. In addition, the Gresham products CT2C Rev F and CT2C2 Rev F will support the Hz (Fast-Plus) I 2 C protocol. detailed characterization report for each product is available upon request. CHNGED PRT IDENTIFICTION: While both Gresham and OKI die will be offered under the same OPN, new package marking will be used only for Gresham die, with OKI die marking continuing unchanged. The Gresham die marking reflects the integration of former CSI (Catalyst) into ON Semiconductor, and provides for easier identification of device and die revision, especially for smaller packages with less room for marking. Die origin will also be identified on the packaging box label by the 2-digit wafer fabrication country code of CS: US for Gresham and CS: Japan for OKI. comparative list of current (OKI die) vs. new (Gresham die) marking is presented in the ppendix. Gresham die based sample availability is listed under ffected Devices. Issue Date: 9-ay-200 Rev. 0-Jan-200 Page of 0

4 FIN PRODUCT/PROCESS CHNGE NOTIFICTION # ffected Devices: Part Number (OPN) Samples vail Date Part Number (OPN) Samples vail Date CT2CI-G //200 CT2C0I-G /2/200 CT2CWI-GT //200 * CT2C0WI-GT /2/200 CT2CI-GT //200 CT2C0I-GT /2/200 CT2CHUI-GT //200 CT2C0HUI-GT /2/200 CT2CVP2I-GT //200 CT2C0VP2I-GT /2/200 CT2CZI-GT //200 CT2C0ZI-GT /2/200 CT2CXI-T2 //200 CT2C0TDI-GT /2/200 CT2CE-G //200 CT2C0E-G /2/200 CT2CWE-GT //200 CT2C0WE-GT /2/200 CT2CE-GT //200 CT2C0E-GT /2/200 CT2CHUE-GT //200 CT2C0HUE-GT /2/200 CT2CXE-T2 //200 CT2C0TDE-GT /2/200 CT2C2I-G //200 CT2C0I-G /2/200 CT2C2WI-GT 5/0/200 CT2C0WI-GT /2/200 CT2C2I-GT 5/0/200 CT2C0I-GT /2/200 CT2C2HUI-GT 5/0/200 CT2C0HUI-GT /2/200 CT2C2VP2I-GT 5/0/200 CT2C0VP2I-GT /2/200 CT2C2HUI-GT //200 CT2C0ZI-GT /2/200 CT2C2E-G //200 CT2C0TDI-GT /2/200 CT2C2WE-GT 5/0/200 CT2C0E-G /2/200 CT2C2E-GT 5/0/200 CT2C0WE-GT /2/200 CT2C2HUE-GT 5/0/200 CT2C0E-GT /2/200 CT2C0HUE-GT /2/200 CT2CI-G /2/200 CT2C0TDE-GT /2/200 CT2CWI-GT //200 CT2CI-GT //200 CT2CHUI-GT //200 CT2CVP2I-GT //200 CT2CZI-GT /2/200 CT2CTDI-GT //200 CT2CE-G /2/200 CT2CWE-GT //200 CT2CE-GT //200 CT2CHUE-GT //200 CT2CTDE-GT //200 *Note: imited quantity available now. Issue Date: 9-ay-200 Rev. 0-Jan-200 Page of 0

5 FIN PRODUCT/PROCESS CHNGE NOTIFICTION # EECTRIC CHRCTERISTIC SUR: N/ PRT IDENTIFICTION: ) PDIP D () F R N N N N N R P P P P P P I ON W W G 2 5 : ssembly location code 2: ark for (lead finish NiPdu) : Product Revision -9: Product Name PPPPPP 0: Temp Range (I=Industrial; E=Extended) : Production ear (last digit) 2: Production onth (-9.,B,C) -: ast four digits of assembly lot number -5: Device name (5 char) : Production Revision : ssembly location -0: ssembly ot Number -2: Production ear -: Production Week 5: Pb-free (fixed as G ) Example: CT2CI-G Example: CT2CI-G 2 E 2 C 2 5 F 2 C I ON W W G 2 5 Issue Date: 9-ay-200 Rev. 0-Jan-200 Page 5 of 0

6 FIN PRODUCT/PROCESS CHNGE NOTIFICTION # 2) SOIC -50mil pin (W, V), SOIC 20mil pin (X) F 2 R P P P P P P I : ssembly location code 2: ark for (lead finish NiPdu) : Product Revision -9: Product Name PPPPPP 0: Temp Range (I=Industrial; E=Extended) : Production ear (last digit) 2: Production onth (-9.,B,C) -: ast four digits of assembly lot number -5: Device name (5 char) : Product Revision : ssembly ocation : Production ear 9: Production onth 0-2: ssembly ot Number Pb-Free icrodot Example: CT2CWI-G Example: CT2CWI-G E 2 C F C W I Issue Date: 9-ay-200 Rev. 0-Jan-200 Page of 0

7 FIN PRODUCT/PROCESS CHNGE NOTIFICTION # ) TSSOP- pin () P P P 2 N N N R 2 F : Device name PPP : ssembly ocation 5: ead Finish : Production ear : Production onth 0-2: ssembly ot Number -: Device name ( char) : Product Revision 5: ssembly ocation : Production ear : Production onth -0: ot Number Pb-Free icrodot Example: CT2CI-G Example: CT2CI-G C 2 C F 2 F Issue Date: 9-ay-200 Rev. 0-Jan-200 Page of 0

8 FIN PRODUCT/PROCESS CHNGE NOTIFICTION # ) TDFN 2xmm (VP2) and UDFN 2xmm (HU, HU) P P 2 N N R 2-2: Device name : ssembly ocation -: ot Number : Production ear : Production onth -2: Device code : Code for revision and package : ssembly ocation 5-: ot Number : Production ear : Production onth Pb-Free icrodot Example: CT2CVP2I-G CT2CHUI-G Example: CT2CVP2I-G CT2CHUI-G E P 2 B C 2 C 2 T CT2CHUI-G C U 2 Issue Date: 9-ay-200 Rev. 0-Jan-200 Page of 0

9 FIN PRODUCT/PROCESS CHNGE NOTIFICTION # 5) TSOT-2 5D (TD) P P 2-2: Device code : Production ear : Production onth -2: Device code -: ot Number 5: Production ear : Production onth & ssembly ocation Pb-Free icrodot Bottom Side arking No Bottom Side arking 5 5: ssembly ocation -: ot Number Example (): CT2CTDI-G Example: CT2CTDI-G C 2 5 C Issue Date: 9-ay-200 Rev. 0-Jan-200 Page 9 of 0

10 FIN PRODUCT/PROCESS CHNGE NOTIFICTION # ) SOP D (Z) P P P P 2 N N 2 G 5 5 -: Device code 5: Production ear : Production onth : Product Revision -2: Device code : Production ear : Production onth 5: ssembly ocation -: ssembly ocation Pb-Free icrodot Bottom Side arking NO Bottom Side arking 9 0 : ssembly ocation 9-: ot Number Example (): CT2CZI-G Example: CT2CZI-G B S 2 E 5 C 2 5 Issue Date: 9-ay-200 Rev. 0-Jan-200 Page 0 of 0