EE382V: Embedded System Design and Modeling

Transcription

1 EE382V: Embedded System Design and Methodologies, Models, Languages Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin : Outline Methodologies Design flows Bottom-up, top-down, meet-in-the-middle, platform-based System design flow System design languages Goals, requirements Communication and computation EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 2 (c) 2011 A. Gerstlauer 1

2 Evolution of Design Flows Capture & Simulate Describe & Synthesize Specify, Explore & Refine Specs Specs Executable Spec Functionality Algorithms Algorithms Algorithms Algorithms System Gap SW? SW? Architecture Network Connectivity Protocols Design Describe Design SW/HW Performance Simulate Logic Simulate Logic Logic Timing Physical Physical Physical Manufacturing Manufacturing Manufacturing 1960's 1980's 2000's EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 3 Classical System Design Flow System requirement specification system design System architecture design Hardware design hardware software development development Integration & Verification integration & System verification Software development manual (semi)automatic EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 4 (c) 2011 A. Gerstlauer 2

3 Classical Design Cycle Task Specification Fixes in specification HW design Fixes in hardware HW verification SW design Fixes in software SW verification Integration & verification Time EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 5 Electronic System-Level (ESL) Design Flow Hardware design hardware development System requirement specification system design High-level model System-level design Architecture model Integration & Verification integration & System implementation verification Software development software development manual (semi)automatic EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 6 (c) 2011 A. Gerstlauer 3

4 New ESL Design Cycle Task Specification (high-level & arch. models) Fixes in specification HW design Fixes in hardware HW verification SW design Fixes in software SW verification Integration & verification Time EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 7 Design Flow Design methodology Sequence of design models Flow of transformations between models Models Well-defined, rigorous semantics Systematic flow from specification to implementation Languages Representation of models in machine-readable form EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 8 (c) 2011 A. Gerstlauer 4

5 N N Y Y EE382V: Embedded Sys Dsgn and Y-Chart Behavior (Function) System Processor Structure (Netlist) Models of Computation (MoCs) Specification Algorithm Boolean logic (a v b) Transfer Logic Circuit PE,Bus RTL Gates Transistors Models of Structure (MoSs) Physical (Layout) EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 9 Processor Synthesis Software processor Compilation and linking Hardware processor High-level synthesis BB1 IF PC CMem CW const B1... RF / Scratch pad B2 BB2 BB3 offset AG status address Status ALU MUL Memory IF Algorithm model (program) B3 Microarchitecture model (RTL) EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 10 (c) 2011 A. Gerstlauer 5

6 System Synthesis Structure Partitioning, mapping Timing Scheduling CPU Mem P1 P3 P1 d P3 C1 d P5 Arbiter CPU Bus C1, C2 Bridge C1, C2 Bus P2 P4 C2 P2 P4 P5 HW EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 11 Bottom-Up Methodology Each level generates library for the next higher level Circuit: Standard cells for logic level Logic: RTL components for processor level Processor: Processing and communication components for system level System: System platforms for different applications Floorplanning and layout on each level Behavior (Function) Start System Processor Logic Circuit Physical (Layout) Structure (Netlist) PE,Bus RTL Gates Transistors EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 12 (c) 2011 A. Gerstlauer 6

7 Top-down Methodology Functional description is converted into component netlist on each level Each component function is decomposed further on the next abstraction level Layout is given only for transistor components EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 13 Meet-in-the-Middle Methodology Gate netlist is hand-off Three levels of synthesis System is synthesized with processor components Processor components are synthesized with RTL library RTL components are synthesized with standard cells Two levels of layout System layout is performed with standard cells Standard cells layout with transistors EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 14 (c) 2011 A. Gerstlauer 7

8 Platform-Based Design Meet-in-the-middle at the system level System platform with standard components System design reduced to mapping of specification onto pre-defined platform Behavior (Function) Start System Processor Logic Circuit Physical (Layout) Structure (Netlist) Platform RTL Gates Transistors EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 15 : Outline Introduction Methodologies System design flow System design languages Design example EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 16 (c) 2011 A. Gerstlauer 8

9 System Basis of any design flow and design automation Inputs and outputs of design steps Capability to capture complex systems Precise, complete and unambiguous Models at varying levels of abstraction Level and granularity of implementation detail Speed vs. accuracy Design models as an abstraction of a design instance Representation of some aspect of reality Virtual prototyping for validation through simulation or formal analysis Specification for further implementation/synthesis Describe desired functionality Documentation & specification Abstraction to hide details that are not relevant or not yet known Different parts of the model or different use cases for the same model EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 17 Abstraction Levels unstructured High abstraction untimed Structure Implementation Detail Timing physical layout real time Spatial order Low abstraction Temporal order EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 18 (c) 2011 A. Gerstlauer 9

10 Top-Down Design Flow requirements Product planning constraints pure functional Specification System Design untimed bus functional Architecture timing accurate Processor Design RTL / ISA Implementation cycle accurate gates Logic Design gate delays Structure Timing EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 19 Top-Down Design Flow requirements Product planning constraints pure functional Specification model untimed Computation design partitioned Timed model scheduled Communication design bus functional Transaction-level model timing accurate Processor design RTL / IS Implementation model cycle accurate Structure Logic design Timing EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 20 (c) 2011 A. Gerstlauer 10

11 Top-Down Design Flow requirements Product planning constraints Capture Algor. pure functional Specification model untimed Computation refinement Comp. transaction level Timed model estimated timing Communication refinement Proto. bus functional Transaction-level model timing accurate RTL Hardware synthesis Interface synthesis Software synthesis RTOS Structure RTL / IS Implementation model Logic design cycle accurate Timing EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 21 SpecC Design Methodology System design Validation flow Capture Algor. Specification model Computation refinement Comp. Compilation Validation Analysis Estimation Simulation model Timed model Communication refinement Proto. Compilation Validation Analysis Estimation Simulation model Transaction-level model Compilation Validation Analysis Estimation Simulation model RTL Hardware synthesis Interface synthesis Software synthesis RTOS Backend Implementation model Compilation Validation Analysis Estimation Simulation model EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 22 (c) 2011 A. Gerstlauer 11

12 : Outline Introduction Methodologies System design languages Goals, requirements Communication and computation Design example EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 23 Models vs. Languages Models Poetry Recipe Story State Sequent. machine program Dataflow Languages English Spanish Japanese C C++ Java Recipes vs. English Sequential programs vs. C Computation models describe system behavior Conceptual notion, e.g., recipe, sequential program Languages capture models Concrete form, e.g., English, C Variety of languages can capture one model E.g., sequential program model C,C++, Java One language can capture variety of models E.g., C++ sequential program model, object-oriented model, state machine model Certain languages better at capturing certain models Source: T. Givargis, F. Vahid. Embedded System Design, Wiley EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 24 (c) 2011 A. Gerstlauer 12

13 Text vs. Graphics Models versus languages not to be confused with text versus graphics Text and graphics are just two types of languages Text: letters, numbers Graphics: circles, arrows (plus some letters, numbers) X = 1; if (N) Y = X + 1; X =1 N? Y = X + 1 Source: T. Givargis, F. Vahid. Embedded System Design, Wiley EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 25 Simulation vs. Synthesis Ambiguous semantics of languages Finite state machine case X is when X1=>... when X2=> -- Look-up table Controller Memory Simulatable but not synthesizable or verifiable Impossible to automatically discern implicit meaning Need explicit set of constructs EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 26 (c) 2011 A. Gerstlauer 13

14 Languages Represent a model in machine-readable form Apply algorithms and tools Syntax defines grammar Possible strings over an alphabet Textual or graphical Semantics defines meaning Mapping onto an abstract state machine model Operational semantics Mapping into a mathematical domain (e.g. functions) Denotational semantics Semantic model vs. design models Basic semantic models can represent many design models Discrete event model for hardware and system simulation Design models can be represented in different languages EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 27 Evolution of Design Languages Netlists Structure only: components and connectivity Gate-level [EDIF], system-level [SPIRIT/XML] Hardware description languages (HDLs) Event-driven behavior: signals/wires, clocks Register-transfer level (RTL): boolean logic Discrete event [VHDL, Verilog] System-level design languages (SLDLs) Software behavior: sequential functionality/programs C-based, event-driven [SpecC, SystemC, SystemVerilog] EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 28 (c) 2011 A. Gerstlauer 14

15 System-Level Design Languages (SLDLs) Goals Executability Validation through simulation Synthesizability Implementation in HW and/or SW Support for reuse Modularity Hierarchical composition Separation of concepts Completeness Support for all concepts found in embedded systems Orthogonality Orthogonal constructs for orthogonal concepts Minimality Simplicity Source: R. Doemer, UC Irvine EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 29 System-Level Design Languages (SLDLs) Requirements C C++ Java VHDL Statecharts SystemC Verilog SpecC SpecCharts Behavioral hierarchy Structural hierarchy Concurrency Synchronization Exception handling Timing State transitions Composite data types not supported partially supported supported Source: R. Doemer, UC Irvine EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 30 (c) 2011 A. Gerstlauer 15

16 System-Level Design Languages (SLDLs) C/C++ ANSI standard programming languages, software design Traditionally used for system design because of practicality, availability SystemC C++ API and class library Initially developed at UC Irvine, standard by Open SystemC Initiative (OSCI) SpecC C extension Developed at UC Irvine, standard by SpecC Technology Open Consortium (STOC) SystemVerilog Verilog with C extensions for testbench development Matlab/Simulink Specification and simulation in engineering, algorithm design Unified Language (UML) Software specification, graphical, extensible (meta-modeling) and Analysis of Real-time and Embedded systems (MARTE) profile -XACT XML schema for component documentation, standard by SPIRIT consortium Rosetta (formerly SLDL) Formal specification of constraints, requirements SDL Telecommunication area, standard by ITU Source: R. Doemer, UC Irvine EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 31 Separation of Concerns Fundamental principle in modeling of systems Clear separation of concerns Address separate issues independently System-Level Description Language (SLDL) Orthogonal concepts Orthogonal constructs System-level Computation encapsulated in modules / behaviors Communication encapsulated in channels Source: R. Doemer, UC Irvine EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 32 (c) 2011 A. Gerstlauer 16

17 Computation vs. Communication Traditional model Processes and signals Mixture of computation and communication Automatic replacement impossible P1 s1 s2 s3 P2 SpecC model Behaviors and channels Separation of computation and communication Plug-and-play Source: R. Doemer, UC Irvine EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 33 B1 C1 v1 v2 v3 B2 Computation vs. Communication Protocol Inlining Specification model Exploration model B1 C1 v1 v2 B2 v3 Computation in behaviors Communication in channels Implementation model B1 Channel disappears Communication inlined into behaviors Wires exposed v1 v2 v3 B2 Source: R. Doemer, UC Irvine EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 34 (c) 2011 A. Gerstlauer 17