EE382V: Embedded System Design and Modeling

Transcription

1 EE382V: Embedded System Design and Class Introduction Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin : Outline Introduction Embedded systems System-level design Course information Administration Topics Materials Policies Projects EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 2 (c) 2011 A. Gerstlauer 1

2 Embedded Systems Systems that are part of a larger system Application-specific Diverse application areas Tight constraints Real-time, performance, power, size Cost, time-to-market, reliability Ubiquitous Far bigger market than generalpurpose computing (PCs, servers) $46 billion in 04, >$90 billion by 2010, 14% annual growth 4 billion devices in 04 98% of all processors sold [Turley02, embedded.com] EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 3 System Design is hard EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 4 (c) 2011 A. Gerstlauer 2

3 and getting harder Growing system complexities Increasing application demands Networked and distributed Cyber-physical integration Increasingly programmable & customizable Technological advances Multi-Processor System-On-Chip (MPSoC) 10, ,000 Logic transistors per chip (in millions) 1, IC capacity Productivity Gap 10, Productivity (K) Trans./Staff-Mo Source: SEMATECH; Courtesy of: T. Givargis, F. Vahid. Embedded System Design, Wiley EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 5 General-Purpose Computing Reaching physical limits of technology scaling Power/utilization/ walls and dark silicon Efficiency/optimality vs. flexibility/generality Opportunity and need for specialization Heterogeneous multi-core / Asynchronous CMP GP-GPUs EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 6 (c) 2011 A. Gerstlauer 3

4 Processor Implementation Options Source: T. Noll, RWTH Aachen, via R. Leupers, From ASIP to MPSoC, Computer Engineering Colloquium, TU Delft, 2006 EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 7 Multi-Processor System-on-Chip (MPSoC) System Memory Memory Controller CPU GPU Local RAM Frontside Bus DSP DSP RAM Hardware Accelerator Bridge DSP Bus Shared RAM Hardware Accelerator Video Front End Local Bus EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 8 (c) 2011 A. Gerstlauer 4

5 MPSoC Challenges Complexity High degree of parallelism at various levels High degree of design freedom Multiple optimization objectives design constraints Applications Programming Model? Heterogeneity Of components Processors, memories, busses Of design tasks Architecture, mapping, scheduling EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 9 Abstraction Levels Move to higher levels of abstraction [ITRS07, itrs.net] Electronic system-level (ESL) design Level Number of components System System level level 1E0 1E1 Algorithm RTL 1E2 1E3 1E4 Abstraction Accuracy Gate 1E5 1E6 Transistor 1E7 Source: R. Doemer, UC Irvine EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 10 (c) 2011 A. Gerstlauer 5

6 System-Level Design From specification Functionality, behavior Application algorithms Constraints To implementation Architecture Spatial and temporal order Components and connectivity Across hardware and software ARM MP3 Jpeg Requirements, constraints Proc Proc M1 stripe MBUS Proc Proc Proc Computation & communication mapping DSP Enc Dec HW Codebk Design automation at the system level & simulation Synthesis & exploration Verification Implementation (HW/SW synthesis) EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 11 Arbiter1 IP Bridge DCTBus DCT DCT BUS1 (AHB) M1Ctrl DMA TX I/O1 I/O2 BUS2 (DSP) I/O3 I/O4 SI BO BI SO Models and Languages A model: Abstraction of physical reality Mathematical formula, drawing/blueprint, data Core of any design process Specification Define (formally!) desired characteristics Golden reference Documentation Validate and explore design choices Predict before the system is built Contract of what to build Detect problems early (and cheaply) Stimuli A language: Capture a model in machine-readable form Model Simulate or Analyze Results Correctness of model? Accuracy vs. simplicity EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 12 (c) 2011 A. Gerstlauer 6

7 System Specification Capture requirements (what) Functional Free of any implementation details (not how) Non-functional Constraints Natural language Ambiguous Incomplete Formal representation Models of computation Objects & composition rules Concurrency & time Computation & communication Executable Semantics Application development Precise description of desired system behavior Complete and unambiguous EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 13 System Architecture Architecture definition Processing elements (PEs) Processors, memories Communication elements (CEs) Transducers, bus bridges Busses On-chip communication media Arbiter CPU P1 CPU Bus P2 HW P3 P4 C1, C2 Mem Bridge IP Bus C1, C2 P5 IP Virtual platform prototyping Processor simulation for computation Transaction-level modeling (TLM) for communication Design space exploration and mapping Allocation, partitioning, scheduling EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 14 (c) 2011 A. Gerstlauer 7

8 System Implementation Hardware Microarchitecture models Register-transfer level (RTL) Instruction-set simulation (ISS) CPU Software binaries Application object code Real-time operating system (RTOS) Hardware abstraction layer (HAL) System netlist Pins and wires Arbiters, muxes, interrupt controllers (ICs), etc. Bus protocol state machines Specification for further manufacturing Logic synthesis Layout EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 15 System-Level Design Flow CPU Mem B1 B2 v1 Computation & Communication Arbiter Bridge C1 C2 HW Platform library IP System Synthesis Front-End B3 Application specification B4 Instruction-Set Simulator (ISS) Architecture Models TLM n Software // Hardware Synthesis Back-End C-based RTL Software Object Code Hardware VHDL/Verilog EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 16 (c) 2011 A. Gerstlauer 8

9 UT ECE Courses CPU Mem B1 B2 v1 Computation & Communication Arbiter Bridge HW IP Platform library EE382V: Embedded System Design & System Synthesis Front-End C1 B3 C2 Application specification B4 EE382N-4: Adv. Adv. System Architecture Instruction-Set Simulator (ISS) Software Object Code Transaction-Level Models TLM n Software // Hardware Synthesis Back-End EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 17 C-based RTL EE382V: System-on-Chip Design Design Hardware VHDL/Verilog System-On-Chip Environment (SCE) Specification Spec Design Decisions System Design (Specify-Explore-Refine) PE/CE/Bus Database Compile onto platform TLM n TLMn TLMi System models Arch n Archn TLMn RTL DB Hardware Synthesis Software Synthesis SW DB Synthesize target HW/SW HWn.v HWn.v HWn.v RTLn RTLn RTLn ISSn ISSn ISSn Implementation Model CPUn.bin CPUn.bin CPUn.bin Commercial derivative for for Japanese Aerospace Exploration Agency Impl Impl n Impln n EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 18 (c) 2011 A. Gerstlauer 9

10 : Outline Introduction Embedded systems Abstraction levels, design flow System-level design Design tasks, challenges and tools Course information Administration Topics Materials Policies Projects EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 19 Class Administration Schedule Lectures: TTh 3:30-5pm, ENS115 Instructor Prof. Andreas Gerstlauer Office hours: ACE 6.118, T 5-6pm, W 2-3pm, or after class/by appt. Teaching Assistant Parisa Razaghi <parisa.r@mail.utexas.edu> Office hours: TBD Information Web page: Announcements, assignments, grades: Blackboard Questions, discussions: Blackboard EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 20 (c) 2011 A. Gerstlauer 10

11 Course Topics System-level design flow System-level design methodologies System-level design languages (SLDL): SpecC, SystemC Functional modeling System specification Formal Models of Computation (MoC) System synthesis Design space exploration and optimization System-level design tools: SCE Architecture modeling Computation and communication refinement Virtual platform prototyping, transaction-level modeling Prerequisites Software: C/C++ (algorithms and data structures) Hardware: VHDL/Verilog (digital design) Embedded systems and embedded software EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 21 Textbooks (1) Main textbook D. Gajski, S. Abdi, A. Gerstlauer, G. Schirner, Embedded System Design:, Synthesis, Verification, Springer, 2009 ( orange book ) EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 22 (c) 2011 A. Gerstlauer 11

12 Textbooks (2) Optional books A. Gerstlauer, R. Doemer, J. Peng, D. Gajski, System Design: A Practical Guide with SpecC, Kluwer, 2001 ( yellow book ) Practical, example-driven introduction using SpecC T. Groetker, S. Liao, G. Martin, S. Swan, System Design with SystemC, Kluwer, 2002 ( black book") Reference for SystemC language and methodology EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 23 Textbooks (3) Optional books (cont d) E. A Lee, S. Seshia, Introduction to Embedded Systems: A Cyber-Physical Systems Approach, 2011 Background on modeling and implementation F. Vahid, T. Givargis, Embedded System Design: A Unified Hardware/Software Introduction, Wiley, John & Sons, 2001 Background about embedded systems in general Additional reading material posted on class webpage EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 24 (c) 2011 A. Gerstlauer 12

13 Policies Grading Homeworks: 15% Labs: 20% Midterm: 25% Project: 40% No late submissions! Academic dishonesty Homeworks Discuss questions and problems with others Turn in own, independent solution Labs and project Teams of up to 3 students One report and presentation EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 25 Homeworks and Labs Three homeworks and one exam Cover theoretical aspects of system design Languages Models Exploration and optimization Some practical implementation Exposure to general language and modeling concepts Two labs Real-world system design Digital camera example on ARM-based platform Using System-on-Chip Environment (SCE) From specification to implementation Design space exploration EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 26 (c) 2011 A. Gerstlauer 13

14 Project Project goals Either research or implementation project System design research problem Literature survey on system design research area System design example/case study Literature review, proposal, implementation Final report and presentation in publishable quality Project timeline (tentative) Abstract: September 30 Proposal, literature survey: November 1 Presentations: last week of classes (Nov. 29 & Dec 1) Report: finals week (Dec. 6) EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 27 Some Possible Projects Design projects (Embedded) system design example Specify, model, simulate, explore, synthesize using SCE Research projects and languages Specification modeling» Develop/modify a language or MoC: data parallel extensions of SpecC/SystemC» Translation between MoCs & languages: from Matlab/SDF/ to SpecC/SystemC Architecture modeling» Component modeling: QEMU-SpecC/SystemC integration, bus modeling» Automatic model generation: generate bus TLMs from abstract protocol descriptions» OS modeling: OS-internal timing estimation and back-annotation» Performance estimation and modeling (timing, power, reliability, ): statistical simulation, parallel or hardware/software co-simulation of functional & performance models» Assertion-based verification in a TLM environment Synthesis Pick an implementation problem and solve it» Decision making: machine learning for optimization (allocation, partitioning, scheduling), design space exploration for dataflow models/signal processing systems» OS scheduling for power, performance, reliability» Hardware or software synthesis for new OS/processors: targeting Linux in SCE EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 28 (c) 2011 A. Gerstlauer 14

15 Successful Past Projects A. Abdel-Hadi, J. Michel, "Real-Time Optimization of Video Transmission in a Network of AAVs," VTC A. Pedram, C. Craven, T. Amimeur, Cache Effects at the Transaction Level, IESS 2009 (best paper runner-up) A. Banerjee, Transaction Level of Best Effort Channels for Networked Embedded Devices, IESS Exploration and synthesis J. Lin, A. Srivatsa, Heterogeneous Multiprocessor Mapping for Real-Time Streaming Systems, ICASSP EE382V: Embedded Sys Dsgn and, 2011 A. Gerstlauer 29 (c) 2011 A. Gerstlauer 15