EE382N.23: Embedded System Design and Modeling

Transcription

1 EE382N.23: Embedded System Design and Modeling Lecture 7 System Refinement & Modeling Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu Lecture 7: Outline System-level synthesis Design flow: From specification to implementation X-Chart: Decision making + refinement System-level refinement Refinement flow & process Refinement example System-level modeling Virtual protoyping & virtual platform models EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 1

2 System-Level Design Flow Structure Partitioning System Processor Timing Scheduling CPU Mem P1 P3 P1 d P3 C1 d P5 Arbiter CPU Bus C1, C2 Bridge C1, C2 IP Bus P2 P4 C2 P2 P4 P5 HW IP EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 3 Application Specification (MoC) P1 P2 Computation Processes Communication Channels Variables C2 C1 P3 P4 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 2

3 Platform Architecture Template CPU1 Mem Components: Processors Memories IPs, custom HW Buses, bridges Arbiter Bridge HW IP CPU2 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 5 System Definition CPU P1 P2 OS Mem Mapping decisions: Allocation Partitioning Scheduling Arbiter C1 C2 Bridge P3 OS P4 HW CPU2 System Definition = Application + Platform + Mapping EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 3

4 Architecture Model CPU1 P1 OS P2 Mem TX Computation Processing elements Communication Busses Bridges/transducers Bus1 Bus2 P3 OS P4 HW CPU2 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 7 Backend Hardware/Software Synthesis CPU1 Program EXE RTOS HAL Compile RTOS/ Driver Synthesis P1 P2 OS HAL TX Bus1 Bus2 C-to-RTL Synthesis P3 Program EXE RTOS HAL HW IP Processes in C CPU2 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 4

5 Implementation Model CPU1 Program EXE IC Mem Arbiter RTOS HAL Interface HW IP Program EXE RTOS HAL CPU2 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 9 System Design Evolution Present Past Platform HW Dev. Board SW Dev. Board App. Dev. Prototype + BSP Platform Platform Modeling VP Virtual Platform SW Dev. HW Dev. Board + BSP App. Dev. Prototype Future Application Developer C/MoC Platform Sys. Gen. VP SW Gen. HW Gen. Board + BSP + App ASIC/ FPGA Tools Prototype Source: S. Abdi, Concordia Univ. EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 5

6 Synthesis Gajski s Y-Chart Behavior System Synthesis Processor Structure Logic EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 11 Synthesis Gajski s Y-Chart Behavior Structure EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 6

7 Synthesis Gajski s Platform-based Y-Chartdesign (the other Y Chart) Behavior / Function Architecture Constraints Structure EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 13 Synthesis X-Chart Behavior / Function Specification Architecture Constraints Structure Implementation Quality EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 7

8 Synthesis X-Chart System-Level Synthesis Model of Computation (MoC) Specification Model Platforms, IP Databases Behavior Architecture Synthesis Decision Making Refinement Transaction- Level Model (TLM) Implementation Model Structure Quality Hardware/Software Synthesis Performance Estimates Source: A. Gerstlauer, C. Haubelt, A. Pimentel, et al., Electronic System-Level Synthesis Methodologies, TCAD, EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 15 Hardware vs. Software Double-roof model Software system Hardware task component Specification instruction architecture logic ISA RTL Arch Implementation gate Source: A. Gerstlauer, C. Haubelt, A. Pimentel, et al., Electronic System-Level Synthesis Methodologies, TCAD, EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 8

9 Lecture 7: Outline System-level synthesis Design flow: From specification to implementation X-Chart: Decision making + refinement System-level refinement Refinement flow & process Refinement example System-level modeling Virtual protoyping & virtual platform models EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 17 System-Level Synthesis X-Chart Behavior (MoC) Decision Making Structure (TLM) Specification Synthesis Constraints (Architecture) Implementation Refinement Quality (Metrics) Specification Methodology Stepwise model refinement Computation & communication Implementation Hardware/Software Synthesis EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 9

10 Synthesis & Refinement Flow Synthesis = Decision making + model refinement GUI Specification model Model n Synthesis algorithm Design decisions Refinement DB Model n+1 Implementation model Successive, stepwise model refinement Layers of implementation detail EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 19 Refinement unstructured High abstraction untimed Structure Implementation Detail Timing physical layout real time Spatial order Low abstraction Temporal order EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 10

11 Modeling Basis of any design flow and design automation Inputs and outputs of design steps Capability to capture complex systems Precise, complete and unambiguous Models at varying levels of abstraction Level and granularity of implementation detail Speed vs. accuracy Design models as an abstraction of a design instance Representation of some aspect of reality Virtual prototyping for validation through simulation or formal analysis Specification for further implementation Describe desired functionality Documentation & Specification (Simulation & Synthesis) Abstraction to hide details that are not relevant or not yet known Different parts of the model or different use cases for the same model EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 21 Computation vs. Communication System design flow Path from model A to model F Cycletimed D F Communication Approximatetimed C E A. System specification model B. Timed functional model C. Architecture model D. Pin-/bus cycle-accurate model (P/BCAM) E. Computation cycle-accurate model (CCAM) F. Cycle-accurate implementation model (CAM) Cycletimed Untimed A B Untimed Approximatetimed Computation Source: L. Cai, D. Gajski. Transaction level modeling: An overview, ISSS 2003 Design methodology and modeling flow Set of models and transformations between models EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 11

12 SpecC Design Flow requirements Product planning constraints Capture Algor. IP pure functional Specification model untimed Computation refinement Comp. IP transaction level Computation model estimated timing Communication refinement Proto. IP bus functional Communication model timing accurate RTL IP Hardware synthesis Interface synthesis Software synthesis RTOS IP Structure RTL / IS Implementation model Logic design cycle accurate Timing EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 23 Validation Flow System Design Functional and timing validation Capture Algor. IP Specification model Computation refinement Comp. IP Compilation Validation Analysis Estimation Simulation model Computation model Communication refinement Proto. IP Compilation Validation Analysis Estimation Simulation model Communication model Compilation Validation Analysis Estimation Simulation model RTL IP Hardware synthesis Interface synthesis Software synthesis RTOS IP Backend Implementation model Compilation Validation Analysis Estimation Simulation model EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 12

13 Validation Levels Requirements (attributes + constraints) Specification (untimed) Functionality SpecC (SW+HW) Computation (execution delays) Communication (timed) Architecture Protocols Implementation (cycle-accurate: RTL+IS) Micro-architecture Gate Level (sub-cycle delays) Clock cycle Layout (continuos time) Spacing Manufacturing (real time) Structure & Timing EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 25 Virtual Platform Prototyping Computation refinement Untimed Architecture Implementation Virtual Prototype Communication refinement Source: C. Haubelt, Univ. of Rostock EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 13

14 Virtual Prototyping Speed vs. Accuracy Discrete-event simulation speed Proportional to number of simulated events Proportional to granularity of simulated time/detail Real-time : simulated vs. simulation time > 1 Discrete-event simulation accuracy Proportional to simulated implementation order Inversely proportional to simulated granularity Where order matters (structural concurrency) Fundamental modeling tradeoff Accuracy Refinement Speed PE0 Simulated time t 0 t 1 t 2 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 27 Lecture 7: Outline System-level synthesis Design flow: From specification to implementation X-Chart: Decision making + refinement System-level refinement Refinement flow & process Refinement example System-level modeling Virtual protoyping & virtual platform models EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 14

15 Specification Model Example B1 B1 B2 c2 B3 Synthesizable specification model Hierarchical parallel-serial composition Communication through variables and standard channels EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 29 Computation Refinement PE allocation / selection Behavior partitioning Variable partitioning Scheduling Specification model Computation refinement Computation model Communication refinement Communication model Processor refinement Implementation model EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 15

16 PE Allocation, Behavior Partitioning B1 B1 Allocate PEs PE2 Partition behaviors B2 c2 B3 Globalize communication Additional level of hierarchy to model PE structure EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 31 Model after Behavior Partitioning B1 B1 PE2 B13snd cb13 B13rcv B2 c2 B3 B34rcv cb34 B34snd Synchronization to preserve execution order/semantics EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 16

17 Variable Partitioning Shared memory vs. message passing implementation Map global variables to local memories Communicate data over message-passing channels B1 B1 PE2 B13snd cb13 B13rcv B2 c2 B3 B34rcv cb34 B34snd EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 33 Model after Variable Partitioning B1 B1 PE2 B13snd cb13 B13rcv B2 c2 B3 B34rcv cb34 B34snd Keep local variable copies in sync Communicate updated values at synchronization points Transfer control & data over message-passing channel EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 17

18 Timed Computation Execution time of behaviors Estimated target delay / timing budget Granularity Behavior / function / basic-block level Annotate behaviors Simulation feedback Synthesis constraints 1 5 behavior B2( in int, ISend c2 ) { void main(void) { waitfor( delay1 B2_DELAY1 ); ); c2.send( ); 10 } }; waitfor( B2_DELAY2 ); EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 35 Scheduling Serialize behavior execution on components B1 B1 B2 B13snd B34rcv Static scheduling Fixed behavior execution order Flattened behavior hierarchy Dynamic scheduling Pool of tasks Scheduler, abstracted OS EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 18

19 Computation Model Example PE2 B1 B1 B13snd B2 cb13 c2 B13rcv B3 B34rcv cb34 B34snd EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 37 Computation Model Component structure/architecture Top level of behavior hierarchy Behavioral/functional component view Behaviors grouped under top-level component behaviors Sequential behavior execution Timed Estimated execution delays Specification model Computation refinement Computation model Communication refinement Communication model Processor refinement Implementation model EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 19

20 Communication Refinement Network allocation / protocol selection Channel partitioning Protocol stack insertion Inlining Specification model Computation refinement Computation model Communication refinement Communication model Processor refinement Implementation model EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 39 Network Allocation / Channel Partitioning PE2 B1 B1 Bus1 Allocate busses B13snd cb13 B13rcv Partition channels B2 c2 B3 Update communication B34rcv cb34 B34snd Additional level of hierarchy to model bus structure EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 20

21 Model after Channel Partitioning B1 B1 PE2 B13snd B2 Bus1 cb13 c2 cb34 B13rcv B3 B34rcv B34snd EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 41 Protocol Insertion Bus1 cb13 c2 cb34 Bus1 Network Protocol Layer Layers Insert protocol layer Bus protocol channel from database Create network layers Implement message-passing over bus protocol Replace bus channel Hierarchical combination of complete protocol stack EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 21

22 Model after Protocol Insertion Master Slave PE2 B1 B1 Bus1 B13snd B2 IBusMaster IProtocolMaster BusProtocol addr[16] data[32] ready ack IProtocolSlave IBusSlave B13rcv B3 B34rcv B34snd EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 43 Inlining: Transaction-Level Model (TLM) Bus1 PE2 BusProtocol IBusMaster IProtocolMaster addr[16] data[32] ready ack IProtocolSlave IBusSlave Create bus interfaces and drivers Bus BusProtocolTLM PE2Bus PE2 IBusMaster IProtocolMaster read()/write() methods in C, functionality + timing IProtocolSlave IBusSlave EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 22

23 Inlining: Pin-Accurate Model (PAM) Bus1 PE2 BusProtocol IBusMaster IProtocolMaster addr[16] data[32] ready ack IProtocolSlave IBusSlave Bus IBusMaster IBusMaster IProtocolMaster Protocol Create bus interfaces and drivers Refine communication IProtocolMaster BusProtocolTLM address[15:0] Transaction-Level data[31:0] Model (TLM) control IProtocolSlave PE2Bus PE2Protocol IProtocolSlave IBusSlave IBusSlave PE2 EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 45 Communication Model Example PE2 B1 B1 B2 B13snd address[15:0] data[31:0] control B13rcv B3 B34rcv B34snd EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 23

24 Communication Model Component & bus structure/architecture Top level of hierarchy Bus-functional component models Timing-accurate bus protocols Behavioral component description Timed Estimated component delays Timing-accurate communication Transaction-level model (TLM) Pin-accurate model (PAM) Bus cycle-accurate model (BCAM) Specification model Computation refinement Computation model Communication refinement Communication model Processor refinement Implementation model EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 47 Processor Refinement Specification model Cycle-accurate implementation of PEs Hardware synthesis down to RTL Software synthesis down to IS Interface synthesis down to RTL/IS Computation refinement Computation model Communication refinement Communication model Processor refinement Implementation model EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 24

25 Hardware Synthesis PE2 B13rcv B3 PE2_CLK PE2_CLK PE2_CLK Clock boundaries B34snd Schedule operations into clock cycles Define clock boundaries in leaf behavior C code Create FSMD model from scheduled C code Controller + datapath EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 49 Software Synthesis B1 Ff2 MOVE r0, r1 B13snd B2 SHL ADD INC PUSH CALL POP r3 r2, r3, r4 r2 r1 Ff3 r0 B34rcv Implement behavior on processor instruction-set Code generation Compilation EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 25

26 Interface Synthesis S0 Bus PE2Bus S1 S2 S3 IBusMaster IProtocolMaster Protocol addr[15:0] data[31:0] ready ack addr[15:0] data[31:0] ready ack PE2Protocol IProtocolSlave IBusSlave DRV S4 Implement communication on components Hardware bus interface logic Software bus drivers EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 51 Implementation Model Software processor Custom hardware PE2 OBJ PORTA address[15:0] S0 Instruction Set Simulator (ISS) PORTB PORTC INTA data[31:0] ready ack S1 S2 S3 S4 _CLK PE2_CLK EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 26

27 Implementation Model Cycle-accurate system description RTL description of hardware Behavioral/structural FSMD view Object code for processors Instruction-set co-simulation Clocked bus communication Bus interface timing based on PE clock Specification model Computation refinement Computation model Communication refinement Communication model Processor refinement Implementation model EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 53 Lecture 7: Outline System-level synthesis Design flow: From specification to implementation X-Chart: Decision making + refinement System-level refinement Refinement flow & process Refinement example System-level modeling Virtual protoyping & virtual platform models EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 27

28 System-Level Modeling Space Cycle-Accurate RTL Basic Blocks Instructions Virtual Platform Microarchitecture Semi- Analytical NS - MoC - Network Simulator Model of Computation Tasks MoC NS Messages Packets Words TLM Communication Accuracy Speed Cycles EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 55 Modeling Levels Host-compiled ISS Functions Blocks/stmnts. Instructions Pipeline Application Algorithm Networking Assembly code Driver μarch Protocol RTL Messages Packets Words Cycles P-TLM N-TLM Host-compiled modeling Transaction-level modeling of computation (TLM) of communication Abstract execution above Abstract transactions above instructions pins and wires Native execution of Function calls for data functionality transfer functionality Back-annotation of timing, Back-annotation of timing, energy, energy, Models of execution Models of topology and glue environment (OS & processor) logic EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 28

29 Virtual Platform Models App HW Binary OS P1 P2 P3 Drv P0 App OS Drv HW Interrupts I/O I/F I/O HW HW TLM Bus SLDL Simulation Kernel CPU model Source-level timing, energy,.. backannotation OS & processor models Hardware/IP model Functional model Timing, energy, back-annotation ISS model Cycle-accurate [GEM5] Functional [QEMU] + timing, energy, back-annotation System-level design language (SLDL) & TLM backplane [SpecC, SystemC] EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer 57 Cellphone Example 2 Subsystems ARM7TDMI MP3 Decoding Jpeg Encoding Motorola DSP 56600k GSM Transcoding 4 Accelerator HW blocks 10 I/O HW blocks 5 Busses AMBA AHB DSP Port A bus 3 Custom busses ARM7TDMI Control MP3 JPEG Cust. HW MP3 IN IRQ FIQ PIC INT31... INT0 Cust. HW BMP IN Timer Cust. HW JPEG Output Cust. HW Left SYNTH Cust. HW Keyboard DHS Cust. HW DHS Right SYNTH Cust. HW Display Cust. HW DHS MAD Ouput Cust. HW PCM OUT AMBA AHB Transducer DSP 5660k Encoder Decoder DSP Port A Cust. HW Enc. Input INTD INTC INTB INTA Cust. HW Enc. Output Cust. HW Dec. Input Custom HW Codebook search Cust. HW Dec. Output EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 29

30 Cellphone Results Experimental setup Simulation speed 1.5 second MP3 300 Mcycles/s 640x480 picture Accuracy 1.5 speech GSM <3% error 3s / 300M ARM cycles / 180M DSP cycles Average Error [%] Avg. Error Sim. Time Spec. Appl. Task Arch. Net. FW TLM PAM BFM CAM ISS Transaction-level modeling (TLM) of communication Host-compiled software, OS and processor modeling EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer Simulation Time [s] Lecture 7: Summary System-level synthesis Decision making + refinement System refinement Functionality and performance System modeling Computation and communication EE382N.23: Embedded Sys Dsgn/Modeling, Lecture A. Gerstlauer A. Gerstlauer 30