Parallel Algorithms and VLSI Structures for Median Filtering of Images in Real Time

Transcription

1 Inernaonal Journal of Advanced Research n Compuer Engneerng & Technology (IJARCET) Volume 3 Issue 8 Augus 204 Parallel Algorhms and VLSI Srucures for Medan Flerng of Images n Real Tme Ivan Tsmos Dmyro Peleshko Ivan Izonn Absrac The mos asks of he dgal mage processng requre he mplemenaon of he medan fler n real-me provdng he consrans n erms of he sze and power consumpon The parallel algorhms and srucures for he realzaon of he medan fler whch focused on VLSI echnology are dscussed n hs arcle The auhors formulaed he requremens for he medan fler devces of mages n real me where one of he ways o ensure hem s he hardware mplemenaon of he medan fler wh he exensve use of he dmensonal and emporal parallelzaon and consderaon of recen advances n VLSI echnology Moreover he parallel algorhms of he medan fler for VLSI mplemenaons are analyzed and developed Also he medan fler devce based on hese algorhms s developed and paened where he nroducon of new elemens and relaonshps among hem provdes he performance ncrease n comparson wh he smlar devces The srucures and analycal expressons for evaluang he maor characerscs of he medan fler devces (equpmen coss calculaon me of he medan effecveness) are bul The srucure of conveyor devce s he fases and he mos effecve by he crera of he equpmen use among he consdered srucures of medan fler devces Index Terms bwse comparson mehod nseron sor mehod medan fler devce parallel algorhms VLSI srucures I ITRODUCTIO The mehods and ools for dgal sgnal and mage processng are wdely used n varous felds such as conrol heory medcne varous arfcal nellgence sysems and communcaons facles oher Due o he rapd developmen of echncal means o compeveness requre fas and effcen analyss of sgnals and mages her ransmsson here s a sgnfcan ncrease of he requremens for he processng of dgal mages Complcaons of mahemacal ools for mage analyss makes necessary o mprove exsng and develop new mehods and hgh-speed processng devces ha wll be mee he crera (hardware complexy speed ec) requred by he appled feld of applcaon Manuscrp receved Aug 204 Ivan Tsmos Auomaed Conrol Sysems Deparmen Lvv Polyechnc aonal Unversy Lvv Ukrane Dmyro Peleshko Publshng Informaon Technologes Deparmen Lvv Polyechnc aonal Unversy Lvv Ukrane Ivan Izonn Publshng Informaon Technologes Deparmen Lvv Polyechnc aonal Unversy Lvv Ukrane The selecon useful nformaon from mages whch dsored n dfferen ways s he prmary ask whose soluon s ncreasngly used complex nonlnear flerng echnques ncludng medan fler The purpose of arcle s o develop algorhms and VLSI srucures for medan fler o mprove he rao of performance / hardware coss for echncal devces of sgnal and mage processng for he sysems of arfcal nellgence II MEDIA FILTERIG O THE BASIS OF THE ISERTIO SORT METHOD The srucure of he medan fler devce n real me depends by he frequency of recep numbers and he number of npu channels The conveyer devce wh parallel or sequenal mplemenaon of algorhms s wdely used for quck medan flerng Medan calculaon on he bass of compleely parallel devces s redundan Reduce redundancy can by use of sreamng-conveyor devces wh conssen mplemenaon of algorhms In hese devces calculae of he medan s reduced o he execuon parwse sequence comparson and permuaon of numbers Analyss mehods of sorng shows ha he mos approprae mehod for sreamng-conveyor mplemenaon of medan flerng s nser sor mehod feaure of whch s small me of resul formaon [2] Based on hs mehod we developed a modfed algorhm of medan flerng whch s orened on VLSI mplemenaon [3] Ths algorhm s mplemened based on smulaneous execuon of dencal basc operaons Based on he hardware mplemenaon he basc operaon s realzed by he one processor elemen (PE) The basc operaon of algorhm of he medan flerng s carred ou n wo sages In he frs sep compares he number of В and he number of hs supplemen А ha s sored n PE ( = 2 ) wh he new number of В Н and number of hs supplemen А Н and he resuls of hs comparson are formed by he formulas: 0 when BH B PB () when BH B 0when AH Α PY when AH Α ф (2) where PВ і PY - nformaon on he oupus of he comparson scheme (comparaor) respecvely numbers and dgs of supplemen In he second sage by he resuls for each comparson PE deermned he number В * and he number of hs supplemen А * whch wll be sored here Defnons for each PE number В * and hs numbers ISS: All Rghs Reserved 204 IJARCET 2643

2 Inernaonal Journal of Advanced Research n Compuer Engneerng & Technology (IJARCET) Volume 3 Issue 8 Augus 204 supplemen А * when he number of devces wll be pre-sorng so ha he maxmum s sored n PE and he mnmum - n PE occurs by he formulas: B H when у PB PB PB- PB- PB у -= x B - when PB- у- B B + when у - PB PB PY B when PB PY у - PB у - (3) A x A H when у PB PB PB- PB- PB у -= A - when PB- у- A + when у - PB PB PY A when PB PY у - PB у - (4) where -Y=PY 0 PY PY 2 PY - PY 0 =0 Scheme of he conveyor-sreamng medan flerng devce n whch medan s calculang based on he nseron sor mehod s shown n Fg where Pr - regser; PE - processor elemens; TI - npu for ac mpulses TI The peculary of he consdered srucures s he ably o change sze of he flerng "wndow" hrough seral connecon requred numbers of PE A he same me flerng does no depend on he sze of he "wndow" bu depends on he execuon me of basc operaons whch s: T = Рг + СS+ Км + CCS where Рг СS Км CCS - he response me respecvely by he regser comparson scheme commuaor and conrol commuaor scheme The dealed scheme of he developed and paened medan fler devce can be seen n he nex secon AH BH B Kм B Pг B СSB PB B- B+ B CCS PY A Kм A Pг A PB- СSA A- A+ PB+ A y- PЕ Pr BH Pr AH y PЕ PЕ m+ PЕ med Fgure 2 Scheme of he processor elemen of medan flerng devce whch based on he nseron sor mehod The hardware cos of he medan fler devce based on he nseron sor mehod equals: W = 2 W +W W +W 2W 2W КМ Рr СS СCS Рr Pr where W КМ W Рг W СS W СCS - hardware coss for mplemenaon of devce respecvely by he commuaor regser comparson scheme and conrol commuaor scheme Fgure Algorhmc scheme of he one-dmensonal medan flerng devce whch based on he nseron sor mehod In each ac of work n regsers Pr BH and Pг AH s recorded respecvely new number B Н and he number of hs supplemen A H umbers B Н and A H fed o he npus of all PE Scheme PE shown n Fgure 2 where Kм - commuaor; CS - comparson scheme; CCS - conrol commuaor scheme In each PE usng dagrams СS B and СS A performed comparng numbers B and A wh numbers B H and A H accordng o he formulas () and (2) and are formed her resuls Resul of compare from he oupu of he CS B and CS A processor elemens PЕ - PЕ and PЕ + one comng o he npus of he conrol commuaor scheme PE where conrol commuaor sgnals Kм B and Kм A formng accordng o formulas (3) and (4) Dependng on hs sgnal on he commuaor oupu Kм B (Kм A ) can come eher В Н (А Н ) or В (А ) or В - (А - ) or В + ( А + ) III MEDIA FILTER DEVICE WITH FILTER WIDOW SIZE BASED O THE ISERTIO SORT METHOD Based on he above mehod medan fler devce n he flerng wndow sze m was developed and receved a paen for an nvenon [5] Smlar devces [678] have several dsadvanages whch makes necessary o develop new mage processng echnques n real me For example medan flerng devce [6] conans 2m regsers where (2m ) - number of elemens of sorng n a gven flerng 2 wndow 5( m m) comparson of nodes each conssng of comparson scheme and wo schemes "AD-OR" However hs devce for s realzaon requres large hardware cos and has a low speed whch s deermned by he me of work (2m ) comparson scheme and (2m ) elemens "AD-OR" Closes o he proposed devce s he medan fler devce [7] conanng m regsers where m - wndow sze m adders 2 ( m m) \ 2 m nodes of comparson decoder and ISS: All Rghs Reserved 204 IJARCET 2644

3 Inernaonal Journal of Advanced Research n Compuer Engneerng & Technology (IJARCET) Volume 3 Issue 8 Augus 204 mulplexer However hs devce has a low speed execuon medan flerng whch deermned by he perod of recep of daa dependng on he me of operaon of he regser comparaor adder decoder and mulplexer and s calculaed as follows: f Рг СS SYM D М where f - flraon perod Рг - he me of recordng n he regser СS - he operaon me of comparson scheme SYM - he operaon me of adder D - he operaon me of decoder М - he operaon me of mulplexer In FIG3 s a block dagram of he proposed medan fler devce n FIG 4 shows he node comparson scheme where: - nformaon npu; 2 - npu regser; 3 - node of comparson; 4 - regsers; 5 - comparson node ; 6 - ou of medan; 7 - commuaor; 8 - comparson scheme m (m+)/ (m+)/2 5m 6 Fgure 3 Scheme of he medan flerng devce wh he fler wndow of sze m Fgure 4 Scheme of node of comparson n proposed devce ISS: All Rghs Reserved 204 IJARCET 2645

4 Inernaonal Journal of Advanced Research n Compuer Engneerng & Technology (IJARCET) Volume 3 Issue 8 Augus 204 Ths devce provdes performance of medan flerng wh ac: Рг СS Км where Рг - Рг - he me of recordng n he regser СS СS - he operaon me of comparson scheme Км - he operaon me of commuaor IV MEDIA FILTERIG O THE BASIS OF THE BITWISE COMPARISO METHOD One of he medan flerng algorhms on he bass of he bwse comparson mehod s algorhm where medan s calculaed sequenally b from b begn from hgh b Calculaon each b of medan mplemens n wo seps In he frs sep we calculae і-h value where =2n b of medan as: y x m when when 0 x m where x - -h rank of he -h number In he nex sep dependng on he value of y s done modfcaon nex bs as follows: k k m (5) x x y x y x y x (6) where k=+ n The srucure of devce ha mplemens hs algorhm s shown n Fg 5 where MI A - many npus adder; SMR - scheme of modfcaon bs PЕ PЕ + Pr n + Pr 2 n + Pr n + Pr m - MI A SМР SМР 2 SМР СS PЕ n med Fgure 5 Srucure of medan fler wh conssen calculaon of medan bs The devce consss of n dencal PE for each of hem s calculaed one b of medan y wh he formula (5) and s modfed nex b of numbers wh he formula (6) Medan value s obaned a he oupu PEn afer passng hrough all he numbers of PE The devce works on he conveyor prncple wh ac whch s: T = рг BСM СS СМD where BСM СS СМD - he operaon me accordng of one-b -npus adder of comparson scheme and of scheme of modfcaon bs The hardware cos for mplemenng medan fler s: W = n W +W +W +W +W 2 рr СМD BСM СS Рr where W BСМ і W СМD - hardware mplemenaon coss accordng for -npus adder and for scheme of modfcaons of bs Anoher mehod of calculang medan of he "wndow" sze =2m+ numbers are fndng as he number of A med for whch m are negers greaer han or equal A med and he same numbers less or equal o A med Calculae he medan of hs mehod s o perform smlar operaons m+ Each operaon nvolves deermnng he maxmum number A pmax n he "wndow" where p=m+ and subsequen modfcaon numbers n hs "wndow" Calculae he maxmum number of A pmax performed by consecuve comparng he bs of all he numbers sarng wh he eldes For each comparson we oban -h b of he maxmum number whch calculaon by he formula: p max p A x y y p (7) where y - -h b of he -h conrol elemen of p-h array Formaon of he -h b ( +)-h of conrol elemens for p-h array s done as follows: y( ) p ( Ap max x ) yp (8) ISS: All Rghs Reserved 204 IJARCET 2646

5 Inernaonal Journal of Advanced Research n Compuer Engneerng & Technology (IJARCET) Volume 3 Issue 8 Augus 204 Afer calculang maxmum number he array modfcaon occurs whch s excluded hs number from he furher process calculaons Ths excepon s made by nverson of he -h bs of n-h conrol elemen: y p пр Ths fler (Fg 6) s mplemened a he (m+) seres-conneced PE each of whch performs a calculaon of y he maxmum number A pmax PE s mplemened on an array of dencal cells xn comparson cell (CP) (Fg 7) Each column of cells CP CP calculaed accordng o he formula (7) he value of -h b maxmum number of A pmax and are formed accordng o formula (8) value (+)-h conrol elemen CP s mplemened on he bass of logc elemens I OR I-o PЕ PЕ Pг PЕ 2 m+ Pг 2 Pг Pг Fgure 6 Scheme of medan fler based on bwse comparson med CP CP 2 CP n CP 2 CP 22 CP 2n CP CP 2 CP n Fgure 7 Scheme for PE of medan fler based on bwse comparson Medan fler can operae n asynchronous and synchronous modes CP schemes for sngle-cycle and conveyor medan fler devces are shown n Fgure 8 a b ISS: All Rghs Reserved 204 IJARCET 2647

6 Inernaonal Journal of Advanced Research n Compuer Engneerng & Technology (IJARCET) Volume 3 Issue 8 Augus 204 x x Tr y p y + p y p C Tr y + p а) b) Fgure 8 Cells comparson scheme: a) sngle-cycle un; b) conveyor devce C In asynchronous mode medan compuaon s done n one ac equal o: T30 3( m ) n where - he operaon me of logc elemen "I" Hardware coss for sngle-ac s medan fler s equal o: W30 3( m ) nw where W hardware coss of he logcal elemens of ype I OR I-OT To ensure he operaon of he medan fler n he synchronous mode s requred n each CP o nclude addonal rggers (Fg 8 B) In synchronous mode medan fler wll operae on a conveyor prncple wh ac equal: T3 k Tг 3 where Tг - he operaon me of rgger Hardware coss for such medan fler are equal o: W3k ( m) n( WTг 3 W) where W Tг - hardware coss for he mplemenaon of he rgger The man componens of he developed srucures of medan fler are regsers swches comparaor and adder The mos approprae s o mplemen developed srucures n he form of VLSI The un of measuremen for equpmen s advsable o logc gae whch s he elemen of nex ype: nverer I OR and o assess emporal parameers - laency logc gae To evaluae he performance of he developed srucures of medan flers used daa on coss and laency of basc componens ha are lsed n [4] Based on hese daa for each of he srucures we developed analycal expressons for calculang he cos of equpmen and me calculaon of medan whch are lsed n he Table where n - dg numbers; = 2m + - he sze of he "wndow" For comparson of developed srucures nroduced esmaon of effcency use of equpmen whch defned as: E WT where: W - equpmen coss for medan fler n valves logcal gaes; T - me for medan calculaon V EVALUATIO FOR THE DEVELOPED STRUCTURES OF MEDIA FILTERS Table Analycal expressons for evaluaon of he man characerscs of he developed srucures for medan fler devces Type of srucure The cos of equpmen (logcal gae) The me of calculang he medan (-gae) Effecveness Fg W =(56n+20)+4n T =(3log 2 n+8) Е =/(3log 2 n+8) [(56n+20)+4n] Fg3 W 2 =9n 2 +0n 2 +8 T 2 =(7log 2 +3log 2 n+5) Е 2 =/(7log 2 +3log 2 n+5) [9n 2 +0n 2 +8] Fg6 W 3o =5 2 n W 3k =4 2 n Graph of he dependence of he effcen use of equpmen from he sze of he "wndow" for n = 8 are shown n Fgure 9 where E E2 - effecve use of equpmen for he devces whch are shown n Fgure Fg 3; E3k E30 - effecve use of equpmen for he devce whch shown n Fg 6 respecvely for conveyor and sngle pulse modes T 3o =5n T 3k =6 Е 3o =/(5n)(5 2 n) Е 3k =/24 2 n The graph shows ha he mos effecve use of he equpmen by he srucure conveyor devce such s shown n Fgure 6 ISS: All Rghs Reserved 204 IJARCET 2648

7 2_ 5_ 9_ 3_ Inernaonal Journal of Advanced Research n Compuer Engneerng & Technology (IJARCET) Volume 3 Issue 8 Augus E E2 E E30 E3k Dr Ivan Tsmos s Professor a Lvv Polyechnc aonal Unversy Ukrane He has publshed more han 00 papers n nernaonal and naonal scenfc ssues and ournals and several books He has auhored more han 80 paens for nvenons and uly models Hs scenfc neress are synhess neural neworks of real-me based on VLSI srucures for sgnal processng n roboc sysems Fgure 9 Graph of he effecve use of equpmen dependng on he sze of he wndow VI COCLUSIO Modulary regulary localy es and parallelsm are he feaures of algorhms and VLSI srucures for medan fler developed n he arcle The applcaon of ppelnng and parallel processng n he desgn of VLSI srucures of medan fler acheves hgh performance Developed and paened medan fler devce exceeds examned analogues n runme of operaons medan flerng wh wndow sze m Among he consdered srucures and devces for medan fler fases and mos effcen use of he equpmen s he conveyor srucure of he devce where medan s deermned by he mehod of he bwse comparson as he number of Amed for whch a "wndow" of sze s /2 numbers greaer or equal A med and he same number smaller or equal o A med REFERECES [] Hrysyk V (988) Parallel processng: Hgh Performance Sysems Parallel processng of nformaon Kev: aukova Dumka [2] Tsmos I Bayuk A Algorhms and daa sorng conveyor devce n real me Vsnyk aonal Unversy "Lvv Polyechnc" [3] Rashkevych Y Tsmos I Bayuk A Fas algorhm and VLSI medan fler srucure Proceedngs of he conference "Drukoeh 96" [4] Tsmos Ivan "Prncples for he developmen and evaluaon of he man characerscs of hgh-performance processors for very large scale negraed crcus " Vsnyk aonal Unversy "Lvv Polyechnc" 349: [5] Y M Rashkevych IG Tsmos DD Peleshko IV Izonn Medan flerng devce UA Paen Aprl [hp://uapaenscom/ prsr-medanno-flrach ml ] [6] Vshenchuk I and V Cherkassky Algorhmc operang devces and supercompuers Kev: Technology 990 [7] Palagn Alexander Reconfgurable compung sysems Fundamenals and Applcaons Kev: Prosva 2006 [ISB ] [8] AL Pereversev One-dmensonal medan fler wh a modular archecure RU Paen July [hp://bdpaensu/ /pa/servl/servleb397h ml] Dr Dmyro Peleshko s Professor a Lvv Polyechnc aonal Unversy Ukrane He has publshed more han 00 papers n nernaonal and naonal scenfc ssues and ournals and he s he auhor of several monographs Hs scenfc neress s dgal mage processng for he sysem of arfcal nellgence He also s a supervsor of four asprans Mr Ivan Izonn s a PhD suden a Lvv Polyechnc aonal Unversy Ukrane He has MSc degree n Auomaed Conrol Sysems and MSc degree n Economc Cybernecs He has publshed several papers n scenfc ournals and has parcpaed n varous nernaonal and naonal conferences Hs research work basedon mprove he qualy of dgal mages ISS: All Rghs Reserved 204 IJARCET 2649