SMV512K32-DB1F0E 16MB SRAM Datasheet

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1 SMV512K32-DB1F0E 16MB SRAM Datasheet 1 Features 2 Summary page 1

2 3 Description 3.1 Figure 1 Block Diagram page 2

3 3.2 Terminal Functions 3.3 Absolute Maximum Ratings page 3

4 3.4 Figure 3 Operating Life Derating Chart 3.5 Recommended Operating Conditions page 4

5 4 Electrical Characteristics page 5

6 5 Operation 5.1 Table 2 SRAM Device Control Operation Truth Table 5.2 Procedures for Controlling the MBE Pin page 6

7 5.3 Table 3 - Example Control Settings for Resetting MBE 5.4 Read Operations 5.5 Table 4 AC Characteristics Read Cycle page 7

8 Table 4 Continued 5.6 Figure 4 SRAM Read Cycle 1, Address-Controlled Access page 8

9 5.7 Figure 5 Read Cycle 2, Chip Enable-Controlled Access 5.8 Figure 6 Read Cycle 3, Output Enable-Controlled Access page 9

10 6 Write Operation with Write-Through Support page 10

11 7 AC Characteristics Write Cycle 7.1 Table 5 AC Characteristics Write Cycle (1) page 11

12 Table 5 Continued 7.2 Figure 7 SRAM Write Cycle 1, WZ Controlled Access page 12

13 7.3 Figure 8 SRAM Write Cycle 1a, WZ-Controlled Write Only with GZ Fixed High page 13

14 7.4 Figure 9 SRAM Write Cycle 2, WZ-Controlled Write with Data Write Through Controlled by GZ page 14

15 7.5 Figure 10 SRAM Write Cycle 3, Enable Controlled Write with Data Write Through Controlled by WZ page 15

16 7.6 Figure 11 SRAM Write Cycle 3a, Enable Controlled Write Only with GZ Fixed High page 16

17 7.7 Figure 12 SRAM Write Cycle 4, Enable Controlled Write with Data Write Through Controlled by GZ 8 Scrub Operation page 17

18 8.1 Table 6 EDAC Control Operation Mode Truth Table 8.2 EDAC Configuration and Scrub Address Polling (Master Device Only) 8.3 Table 7 EDAC Function Select Truth Table (1) page 18

19 8.4 Table 8 EDAC Control Register Programming page 19

20 8.5 Table 9 Scrub Rate Variation page 20

21 8.6 Table 10 BUSYZ Low to SCRUBZ Low Delay Variation page 21

22 8.7 Table 11 AC Characteristics for EDAC Function (1) page 22

23 8.8 Figure 13 Scrub Cycle Controlled by MBE 8.9 Figure 14 Scrub Cycle Controlled by E1Z page 23

24 8.10 Figure 15 Control Register Write Cycle page 24

25 8.11 Figure 16 Control Register Read Cycle page 25

26 8.12 Figure 17 Address Counter Read page 26

27 9 Die Information Chip Dimensions (excluding edge seal and scribe): X: 11,510.8um Y: 16,360.75um Add ~ um to Chip Dimensions X and Y to account for seal ring and scribe. Coordinate system origin (0, 0) is defined by the intersection of lines drawn down and across the outer edges of the metal 5 in the bond pads along the left and bottom edges of the chip (see Figure 18 PAD 1 & 2 Markers). Passivation opening over Bond Pads are um x um. Although 16Mb SRAM die was designed for all bond pads to be wire bonded with 1.0mil bond wire, if package design and wire bond tool capability allows it is recommended for all VSS, VDD1 & VDD2 bond pads to be wire bonded either with bond wire >1.0mil in diameter, or to be double bonded with 1.0mil bond wire. It is not recommended to use bond wire diameters <1.0mil in diameter for any power pads (VSS, VDD!, VDD2). page 27

28 9.1 Figure 18 PAD 1 & 2 Markers page 28

29 9.2 Table 12 - Die Pad Coordinates from Center of Die in Microns Although part was designed to operate properly with single 1.0mil bond wire at all VSS, VDD1 & VDD2 bond pads, if package design and wire bond tool capability allow it is recommended for all VSS, VDD1 and VDD2 bond pads to either use bond wires > 1.0mil in diameter or to be double bonded (two 1.0mil bond wires per VSS, VDD! and VDD2 pad). Origin (0,0) is Lower-Left Corner (see Figure 18)) Pad dimensions are distance from origin (0, 0) to center of bond pad opening. PAD # PAD NAME PAD.X (um) PAD.Y (um) 1 DQ DQ DQ DQ DQ DQ DQ DQ ST0 (VSS) VSS VSS DQ DQ DQ DQ DQ DQ DQ DQ VDD1 (1.8v) A VDD1 (1.8v) A A A A page 29

30 PAD # PAD NAME PAD.X (um) PAD.Y (um) 25 A A E1Z GZ E VDD2 (3.3v) A VDD2 (3.3v) ST1 (VSS) VSS VSS SCRUBZ BUSYZ MBE VDD2 (3.3v) A VDD2 (3.3v) MSS VSS VSS DQ DQ DQ DQ DQ DQ DQ DQ ST2 (VSS) VSS VSS DQ DQ DQ DQ DQ DQ page 30

31 PAD # PAD NAME PAD.X (um) PAD.Y (um) 58 DQ DQ VDD1 (1.8v) A VDD1 (1.8v) A A A A A WZ A ST3 (VSS) VSS VSS A A A A A A A ST4 (VSS) VSS VSS page 31

32 9.3 Figure 19 Chip Plot mil 300 mil 200 mil 100 mil 0 mil 644 mil 500 mil 400 mil 300 mil 200 mil 60 60A C05HA512K32 SMV512K32-DB1F0E TOP VIEW A A mil 500 mil 400 mil 300 mil 200 mil 100 mil 0 mil A mil 0 mil 0 mil 100 mil 200 mil 300 mil mil page 32

33 9.4 Figure 20 Bond Pad Signal Order DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 VSS VSS ST2 (VSS) DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VSS VDD1 (1.8v) VSS 39 60A VDD1 (1.8v) MSS A10 VDD2 (3.3v) 37A 62 A9 VDD2 (3.3v) A8 MBE A7 BUSYZ A6 SCRUBZ WZ VSS A18 VSS ST3 (VSS) ST1 (VSS) VSS VDD2 (3.3v) 30A SMV512K32-DB1F0E 70 VSS VDD2 (3.3v) A17 E A5 GZ A4 E1Z A3 A A2 A A1 A A0 A ST4 (VSS) A VSS A VSS VDD1 (1.8v) 20A VDD1 (1.8v) 20 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 ST0 (VSS) VSS VSS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ page 33

34 10 Ordering Information Part Number Environment Package Temperature SMV512K32-DB1F0E Radiation hardened Die -55 C to 125 C SMV512K32HFG (Available from Texas Instruments) Radiation hardened 76-pin HFG -55 C to 125 C page 34

35 11 Revision History Date Version Page Locations Description 3/10/ Initial Release Revision of SMV512K32-DB1F0E Datasheet 3/17/ Added die pad coordinate data 4/20/ Changed address VORAGO Technologies 1501 S MoPac Expressway, Suite #350 Austin, TX info@voragotech.com Phone: (512) page 35

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