CSE/EE 462: VLSI Design Fall The CMOS Fabrication Process and Design Rules. Silicon Wafer. ND Multi-Project Reticle: Rocket Chip.

Transcription

1 Growing the Silicon Ingot CSE/EE 46: VLSI Design Fall 004 The CMOS Fabrication Process and Design Rules Jay Brockman [Adapted from Mary Jane Irwin and Vijay Narananan, CSE Penn State adaptation of Rabaey s Digital Integrated Circuits, 00, J. Rabaey et al.] From Smithsonian, 000 CSE/EE 46 L05 CMOS Fabrication Process and Design Rules. Brockman, ND, 004 CSE/EE 46 L05 CMOS Fabrication Process and Design Rules. Brockman, ND, 004 Silicon Wafer ND Multi-Project Reticle: Rocket Chip Single die Wafer From

2 CMOS Process CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers One full photolithography sequence per layer (mask) Built (roughly) from the bottom up 5 metal 4 metal polysilicon exception! source and drain diffusions tubs (aka wells, active areas) CSE/EE 46 L05 CMOS Fabrication Process and Design Rules.5 Brockman, ND, 004 CSE/EE 46 L05 CMOS Fabrication Process and Design Rules.6 Brockman, ND, 004 Photolithographic Process CMOS Inverter oxidation optical mask photoresist removal (ashing) photoresist coating photoresist development stepper exposure process step spin, rinse, dry acid etch

3 P-Type Substrate and N-Well Active Area N-well PMOS devices go here deposited nitride layer P-type substrate NMOS devices go here N-well mask active mask defines p-type and n-type mosfet locations (drain-gate-source) CSE/EE 46 L05 CMOS Fabrication Process and Design Rules.9 Brockman, ND, 004 CSE/EE 46 L05 CMOS Fabrication Process and Design Rules.0 Brockman, ND, 004 Field Oxide Growth Polysilicon Gate o o o o o o o o o o Thick field oxide electrically isolates transistors Nitride prevents field oxide growth Thin gate oxide grown after nitride removed gate oxide SiO formation consumes Si Si-SiO interface below original Si surface field oxide poly mask added to layout

4 P-Select Mask and N-Type Source/Drain Implant N-Select Mask and P-Type Source/Drain Implant n-type implant p-select covers p-type source/drain regions select mask must overlap active areas n-type ion implant creates n-type source/drain regions high temperature anneal repairs silicon lattice and causes diffusion of implanted ions p-type implant finished mosfets both select masks added CSE/EE 46 L05 CMOS Fabrication Process and Design Rules. Brockman, ND, 004 CSE/EE 46 L05 CMOS Fabrication Process and Design Rules.4 Brockman, ND, 004 Contact Cuts Metal non-planar surface

5 Via and Metal Advanced Metallization Multilevel interconnect fabrication processes planarize between layers (expensive) MOSIS SCMOS does not allow stacked vias CSE/EE 46 L05 CMOS Fabrication Process and Design Rules.7 Brockman, ND, 004 CSE/EE 46 L05 CMOS Fabrication Process and Design Rules.8 Brockman, ND, 004 Advanced Metallization A Modern CMOS Process Dual-Well Trench-Isolated CMOS gate oxide field oxide Al (Cu) TiSi SiO tungsten n+ p well p-epi p- n well p+ SiO

6 Design Rules Interface between the circuit designer and process engineer Guidelines for constructing process masks Unit dimension: minimum line width scalable design rules: lambda parameter absolute dimensions: micron rules Rules constructed to ensure that design works even when small fab errors (within some tolerance) occur A complete set includes set of layers intra-layer: relations between objects in the same layer inter-layer: relations between objects on different layers Why Have Design Rules? To be able to tolerate some level of fabrication errors such as. Mask misalignment. Dust. Process parameters (e.g., lateral diffusion) 4. Rough surfaces CSE/EE 46 L05 CMOS Fabrication Process and Design Rules. Brockman, ND, 004 CSE/EE 46 L05 CMOS Fabrication Process and Design Rules. Brockman, ND, 004 Intra-Layer Design Rule Origins Intra-Layer Design Rules Minimum dimensions (e.g., widths) of objects on each layer to maintain that object after fab minimum line width is set by the resolution of the patterning process (photolithography) Minimum spaces between objects (that are not related) on the same layer to ensure they will not short after fab micron 0. micron Well Active Select Same Potential 0 0 or 6 Different Potential 9 Contact or Via Hole Polysilicon Metal Metal 4

7 Inter-Layer Design Rule Origins Transistor Layout. Transistor rules transistor formed by overlap of active and poly layers Transistors Catastrophic error Transistor Unrelated Poly & Diffusion Thinner diffusion, but still working 5 CSE/EE 46 L05 CMOS Fabrication Process and Design Rules.5 Brockman, ND, 004 CSE/EE 46 L05 CMOS Fabrication Process and Design Rules.6 Brockman, ND, 004 Select Layer Inter-Layer Design Rule Origins, Continued Select. Contact and via rules M contact to p-diffusion M contact to n-diffusion M contact to poly Contact Mask Mx contact to My Via Masks 5 both materials 0. Contact: 0.44 x 0.44 mask misaligned 0.4 Substrate Well

8 Vias and Contacts Via 4 5 Metal to Active Contact Metal to Poly Contact CSE/EE 46 L05 CMOS Fabrication Process and Design Rules.9 Brockman, ND, 004